MAX8770GTL+T Maxim Integrated Products, MAX8770GTL+T Datasheet - Page 41

• Manufacturer Part Number: MAX8770GTL+T
• Description: IC CTLR PS 2/1PH QUICK PWM 40QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8770GTL+T

• Applications: Controller, Intel IMVP-6
• Voltage - Input: 4 ~ 26 V
• Number Of Outputs: 1
• Voltage - Output: 0.125 ~ 1.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PWM Controller for IMVP-6+ CPU Core Power Supplies
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feed-back
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is
not enough voltage ramp in the output voltage signal.
This “fools” the error comparator into triggering a new
cycle immediately after the minimum off-time period
has expired. Double pulsing is more annoying than
harmful, resulting in nothing worse than increased out-
put ripple. However, it can indicate the possible pres-
ence of loop instability due to insufficient ESR. Loop
instability can result in oscillations at the output after
line or load steps. Such perturbations are usually
damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
The input capacitor must meet the ripple current
requirement (I
The multiphase Quick-PWM controllers operate out-of-
phase while the Quick-PWM slave controllers provide
selectable out-of-phase or in-phase on-time triggering.
Out-of-phase operation reduces the RMS input current
by dividing the input current between several stag-
gered stages. For duty cycles less than 100%/η
per phase, the I
by the following equation:
where η
switching regulators. The worst-case RMS current
requirement occurs when operating with V
2η
fies to I
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resistance to inrush surge currents typical of systems
with a mechanical switch or connector in series with the
input. If the Quick-PWM controller is operated as the
second stage of a two-stage power-conversion system,
tantalum input capacitors are acceptable. In either con-
figuration, choose an input capacitor that exhibits less
than +10°C temperature rise at the RMS input current
for optimal circuit longevity.
I
RMS
TOTAL
=
RMS
V
⎛
⎜
⎝
TOTAL
MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-
OUT
η
TOTAL IN
= 0.5 x I
I
LOAD
. At this point, the above equation simpli-
RMS
RMS
is the total number of out-of-phase
V
______________________________________________________________________________________
) imposed by the switching currents.
⎞
⎟
⎠
LOAD
requirements may be determined
Input Capacitor Selection
η
TOTAL OUT IN
/η
TOTAL
V
.
(
V
−
η
TOTAL OUT
V
OUTPH
IN
)
=
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-cur-
rent applications usually require less attention.
The high-side MOSFET (N
the resistive losses plus the switching losses at both
V
Ideally, the losses at V
to losses at V
the losses at V
losses at V
(reducing R
if the losses at V
losses at V
(increasing R
vary over a wide range, the minimum power dissipation
occurs where the resistive losses equal the switching
losses.
Choose a low-side MOSFET that has the lowest possi-
ble on-resistance (R
sized package (i.e., one or two 8-pin SOs, DPAK, or
D
DL gate driver can supply sufficient current to support
the gate charge and the current injected into the para-
sitic gate-to-drain capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction prob-
lems may occur (see the MOSFET Gate Driver section).
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N
case power dissipation due to resistance occurs at the
minimum input voltage:
where η
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (R
side switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation the in high-side MOS-
FET (N
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold volt-
IN(MIN)
PD N
2
PAK), and is reasonably priced. Make sure that the
(
H
H
TOTAL
) due to switching losses is difficult since it
and V
Re
IN(MAX)
IN(MIN)
DS(ON)
sistive
DS(ON)
IN(MAX)
is the total number of phases.
IN(MAX)
IN(MIN)
DS(ON)
IN(MAX)
, consider increasing the size of N
, consider reducing the size of N
)
but with higher C
MOSFET Power Dissipation
®
=
, with lower losses in between. If
to lower C
DS(ON)
Power MOSFET Selection
. Calculate both of these sums.
IN(MIN)
are significantly higher than the
required to stay within package
⎛
⎜
⎝
IMVP-6 LICENSEES
are significantly higher than the
V
OUT
V
H
IN
) must be able to dissipate
), comes in a moderate-
should be roughly equal
⎞
⎟
⎠
GATE
⎛
⎜
⎝
DS(ON)
η
I
LOAD
TOTAL
GATE
). If V
) losses. High-
). Conversely,
H
⎞
⎟
⎠
), the worst-
2
IN
R
does not
DS ON
(
41
)
H
H