MAX1809EEE+T Maxim Integrated Products, MAX1809EEE+T Datasheet - Page 11

• Manufacturer Part Number: MAX1809EEE+T
• Description: IC DDR TERMINATION 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1809EEE+T

• Applications: Converter, DDR
• Voltage - Input: 3 ~ 5.5 V
• Number Of Outputs: 1
• Voltage - Output: 1.1 ~ 5.5 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The output current limit during soft-start varies with
the voltage on the soft-start pin, SS, according to the
equation:
where I
Electrical Characteristics. The constant-current source
stops charging once the voltage across the soft-start
capacitor reaches 1.8V.
The operating frequency of the MAX1809 is determined
primarily by t
shown in the following formula:
However, as the output current increases, the voltage
drop across the NMOS and PMOS switches increases
and the voltage across the inductor decreases. This
causes the frequency to drop. Assuming R
R
with the following formula:
where R
(90mΩ typ).
Good layout is necessary to achieve the MAX1809’s
intended output power level, high efficiency, and low
noise. Good layout includes the use of ground planes,
Figure 5. Adjusting the Output Voltage Using EXTREF
(1.1V ≤ V
NMOS
Frequency Variation with Output Current
EXTREF
, the change in frequency can be approximated
LIMIT
PMOS
≤ V
IN
3A, 1MHz, DDR Memory Termination Supply
V
f
SW
- 1.7V)
EXTREF
OFF
is the resistance of the internal MOSFETs
is the current-limit threshold from the
V
I
=
LIM SS
∆
DDQ
Applications Information
f
t
SW
Circuit Layout and Grounding
OFF IN
______________________________________________________________________________________
(
(set by R
EXTREF
(
=
V
)
(
IN
V
MAX1809
=
∆
I
OUT
(
−
V
V
V
−
SS
IN
OUT
V
1 1
PMOS
TOFF
×
×
−
.
t
R
LX
FB
0 7
V
OFF
−
PMOS
.
V
), V
V
PMOS
+
)
V
×
NMOS
IN
I
LIMIT
, and V
)
)
V
OUT
PMOS
OUT
= V
EXTREF
as
=
careful component placement, and correct routing of
traces using appropriate trace widths. The following
points are in order of decreasing importance:
1) Minimize switched-current and high-current ground
2) Connect the input filter capacitor less than 5mm
3) Place the LX node components as close together
4) Ground planes are essential for optimum perfor-
In applications where the load transients are extremely
fast (>10A/µs), the total output capacitance has to be
large enough to handle the V
ments while keeping within the output tolerance limits.
Voltage positioning reduces the total amount of output
capacitance needed to meet a given transient
response requirement. With voltage positioning, the
Figure 6. Adjusting the Output Voltage at FB
loops. Connect the input capacitor’s ground, the
output capacitor’s ground, and PGND close together.
Connect the resulting PGND plane to GND at only
one point.
away from IN. The connecting copper trace carries
large currents and must be at least 1mm wide,
preferably 2.5mm.
and as near to the device as possible. This reduces
resistive and switching losses as well as noise.
mance. In most applications, the circuit is located on
a multilayer board and full use of the four or more
layers is recommended. For heat dissipation, con-
nect the exposed backside pad of the QFN pack-
age to a large analog ground plane, preferably on a
surface of the board that receives good airflow. If
the ground plane is located on the top layer, make
use of the N.C. pins adjacent to GND to lower thermal
resistance to the ground plane. If the ground is
located elsewhere, use several vias to lower thermal
resistance. Typical applications use multiple ground
planes to minimize thermal resistance. Avoid large
AC currents through the analog ground plane.
R2 = R1[(V
EXTREF
MAX1809
OUT
/ V
EXTREF
LX
FB
) - 1]
Voltage Positioning
SAG
and V
SOAR
R2
R1
V
OUT
require-
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