ADP3209CJCPZ-RL ON Semiconductor, ADP3209CJCPZ-RL Datasheet - Page 16

• Manufacturer Part Number: ADP3209CJCPZ-RL
• Description: IC CTLR BUCK 5BIT 1PH 32LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3209CJCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.4 ~ 1.25 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VOLTAGE CONTROL MODE
A high-gain bandwidth error amplifier is used for the voltage
mode control loop. The noninverting input voltage is set via the
5-bit VID DAC. The VID codes are listed in Table 4. The
noninverting input voltage is offset by the droop voltage as a
function of current, commonly known as active voltage
positioning. The output of the error amplifier is the COMP pin,
which sets the termination voltage of the internal PWM ramps.
At the negative input, the FB pin is tied to the output sense
location using R
output voltage at the remote sensing point. The main loop
compensation is incorporated in the feedback network
connected between the FB and COMP pins.
POWER-GOOD MONITORING
The power-good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output that
can be pulled up through an external resistor to a voltage rail—
not necessarily the same VCC voltage rail that is running the
controller. A logic high level indicates that the output voltage is
within the voltage limits defined by a range around the VID
voltage setting. PWRGD goes low when the output voltage is
outside of this range.
Following the GMCH specification, the PWRGD range is
defined to be 300 mV less than and 200 mV greater than the
actual VID DAC output voltage. To prevent a false alarm, the
power-good circuit is masked during any VID change and
during soft start. The duration of the PWRGD mask is set to
approximately 100 µs by an internal timer. In addition, for a
VID change from high to low, there is an additional period of
PWRGD masking before the voltage of the ST pin drops within
200 mV of the new lower VID DAC output voltage, as shown in
Figure 21.
POWER-UP SEQUENCE AND SOFT START
The power-on ramp-up time of the output voltage is set with a
capacitor tied from the SS pin to GND. The capacitance on the SS
pin also determines the current limit latch-off time, as explained in
the Current Limit, Short-Circuit, and
Latch-Off Protection section. The power-up sequence, including the
soft start is illustrated in Figure 22.
VID SIGNAL
CHANGE
ST PIN
VOLTAGE
PWRGD
MASK
Figure 21. PWRGD Masking for VID Change
B
, a resistor for sensing and controlling the
100—s
200mV
100—s
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In VCC UVLO or shutdown mode, the SS pin is held at zero
potential. When VCC ramps to a value greater than the upper
UVLO threshold while EN is asserted high, the ADP3209 enables
the internal bias and starts a reset cycle of about 50 µs to 60 µs.
When the initial reset is complete, the chip signals to ramp up the SS
voltage. During soft start, the external SS capacitor is charged by an
internal 8 µA current source. The V
SS voltage up to the VID code. While the V
VID code voltage, the SS capacitor continues to rise. When the SS
pin voltage reaches 1.7 V, the ADP3209 completes its soft start,
PWRGD asserts high, and the chip switches to normal operation.
If EN is taken low or VCC drops below the lower VCC UVLO
threshold, the SS capacitor is reset to ground to prepare the chip
for a subsequent soft start cycle.
VID CHANGE AND SOFT TRANSIENT
When a VID input changes, the ADP3209 detects the change but
ignores new code for a minimum of 400 ns. This delay is required to
prevent the device from reacting to digital signal skew while the 5-
bit VID input code is in transition. Additionally, the VID change
triggers a PWRGD masking timer to prevent a PWRGD failure.
Each VID change resets and retriggers the internal PWRGD
masking timer.
The ADP3209 provides a soft transient function to reduce inrush
current during VID transitions. Reducing the inrush current helps
decrease the acoustic noise generated by the MLCC input capacitors
and inductors.
The soft transient feature is implemented with an ST buffer
amplifier that outputs constant sink or source current on the ST pin
that is connected to an external capacitor. The capacitor is used to
program the slew rate of V
transient. During steady-state operation, the reference inputs of the
voltage error amplifier and the ST amplifier are connected to the
VID DAC output. Consequently, the ST voltage is a buffered version
of VID DAC output. When a VID change triggers a soft transition,
the reference input of the voltage error amplifier switches from the
DAC output to the ST output while the input of the ST amplifier
V
V
PWRGD
SS
CCGFX
Figure 22. Power-Up Sequence of ADP3209
V5_S
GFXCORE_EN
CCGFX
1.7V
voltage during a VID voltage
2.9V
CCGFX
PGDELAY
voltage follows the ramping
CCGFX
is regulated at the