ISL6266AIRZ-T Intersil, ISL6266AIRZ-T Datasheet - Page 26

• Manufacturer Part Number: ISL6266AIRZ-T
• Description: IC CORE CTRLR 2PHASE 48-QFN
• Manufacturer: Intersil

Specifications of ISL6266AIRZ-T

• Applications: Converter, Intel IMVP-6
• Voltage - Input: 5 ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.3 ~ 1.5 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

R
outputs of all channels together and thus create a summed
average of the local CORE voltage output. R
through an understanding of both the DC and transient load
currents. This value will be covered in the next section.
However, it is important to keep in mind that the outputs of
each of these R
VSUM voltage node. With both the outputs of R
tied together, the simplified model for the droop circuit can
be derived. This is presented in Figure 40.
Figure 40 shows the simplified model of the droop circuitry.
Essentially, one resistor can replace the R
phase and one R
each phase. The total DCR drop due to load current can be
replaced by a DC source, the value of which is given by
Equation 19:
For the convenience of analysis, the NTC network
comprised of R
labeled as a single resistor R
The first step in droop load line compensation is to adjust
R
exists even at light loads between the VSUM and VO' nodes.
As a rule of thumb, we start with the voltage drop across the
R
provides for a fairly reasonable amount of light load signal
from which to arrive at droop.
The resultant NTC network resistor value is dependent on
the temperature and given by Equation 20.
For simplicity, the gain of Vn to the V
G1, also dependent on the temperature of the NTC
thermistor.
Therefore, the output of the droop amplifier divided by the
total load current can be expressed as shown in
Equation 23, where R
and 0.00393 is the temperature coefficient of the copper.
How to achieve the droop value independent of the inductor
temperature is expressed by Equation 24.
V
R
G
DCR T ( )
R
G
O
N
N
DCR_EQU
n
droop
1
1
T ( )
, RO
T ( )
T ( )
network, Vn, to be 0.5x to 0.8x V
is typically 1Ω to 10Ω. This resistor is used to tie the
•
=
EQV
Δ
=
=
(
1
=
(
--------------------------------------------------------------
R
R
G
+
------------------------------------------ -
R
DCR
series
series
1
0.00393*(T-25)
=
n
and RS
T ( )
T ( )
I
-------------------------------- -
OUT
ntc
R
S
25°C
•
+
n
+
S
+
DCR
-------------------
resistors are tied together to create the
, R
T ( )
RS
R
R
resistor can replace the R
•
2
EQV
ntc
ntc
2
•
DCR
series
EQV
droop
(
25
1
) R
+
•
+
•
R
such that sufficient droop voltage
)
0.00393*(T-25)
(
par
and R
≅
1
par
is the realized load line slope
G
+
26
N
1t
0.00393*(T-25)
in Figure 40.
arg
par
et
, given in Figure 37, is
DCR_EQU
DCR_EQU
)
O
resistors of each
) k
S
S
•
is determined
. This ratio
resistors of
is defined by
O
droopamp
and R
ISL6266, ISL6266A
(EQ. 19)
(EQ. 20)
(EQ. 21)
(EQ. 22)
(EQ. 23)
(EQ. 24)
S
The non-inverting droop amplifier circuit has the gain
K
G
Therefore, the temperature characteristics of gain of Vn is
described by Equation 26.
For the G
R
R
R
RS
feature specified in Equation 26.
The actual G1 at +25°C is 0.769. A design file is available to
generate the proper values of R
RS
from the example provided here.
The individual resistors from each phase to the VSUM node,
labeled R
Equation 27.
So, R
and R
gain required to achieve the load line. Setting
R
Droop Impedance (R
IMVP-6+ specification. Using DCR = 0.0008Ω typical for a
0.36µH inductor, R
(G1) = 0.77, R
Note, we choose to ignore the R
not add significant error.
These designed values in R
the layout and coupling factor of the NTC to the inductor. As
only one NTC is required in this application, this NTC should
be placed as close to the Channel 1 inductor as possible and
PCB traces sensing the inductor voltage should route
directly to the inductor pads.
Due to layout parasitics, small adjustments may be
necessary to accurately achieve the full load droop voltage.
This can be easily accomplished by allowing the system to
achieve thermal equilibrium at full load, and then adjusting
R
k
G
Rs
R
R
droopamp
droopamp
ntc
series
par
drp1
drp2
1target
drp2
drp2
1
T ( )
EQV
EQV
=
= 10kΩ with b = 4300,
= 11kΩ
S
2 RS
N
= 1k_1%, then R
to obtain the appropriate load line slope.
=
=
=
•
= 3650Ω. Once we know the attenuation of the R
= 2610Ω, and
= 1825Ω generates a desired G1, close to the
for values of the NTC thermistor and G1 that differ
network, we can then determine the droop amplifier
is the desired gain of Vn over I
⎛
⎝
⎛
⎝
------------------------------------------------------ -
(
S1
1target
1
----------------------------------------------- 1
DCR G1 25°C
-------------------------------------- - 1
0.0008 0.769
=
expressed as Equation 25:
+
2 R
EQV
and R
2 R
0.00393*(T-25)
•
1
drp2
G
•
+
•
1t
droop
= 0.76:
•
R
--------------- -
R
droop
arg
drp2
drp1
S2
drp1
is then given by Equation 29:
(
droop
et
in Figure 37, are then given by
drp2
= 1kΩ and the attenuation gain
–
)
) = 0.0021 (V/A) as per the Intel
⎞
⎠
–
)
can be found using Equation 28.
•
n
⎞
⎠
1kΩ
network are very sensitive to
•
ntc
R
O
drp1
≈
resistors because they do
, R
5.82kΩ
series
OUT
, R
• DCR/2.
par
, and
June 14, 2010
(EQ. 29)
(EQ. 26)
(EQ. 27)
(EQ. 28)
(EQ. 25)
FN6398.3
S