EL5225IRZ-T13 Intersil, EL5225IRZ-T13 Datasheet - Page 8

• Manufacturer Part Number: EL5225IRZ-T13
• Description: IC VREF GEN 10CH TFT-LCD 24TSSOP
• Manufacturer: Intersil

Specifications of EL5225IRZ-T13

• Applications: Converter, TFT, LCD
• Voltage - Input: 5 ~ 16.5 V
• Number Of Outputs: 10
• Voltage - Output: 0.5 ~ 14.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Block Diagram
CHANNEL OUTPUTS
Each of the channel outputs has a rail-to-rail buffer. This
enables all channels to have the capability to drive to within
50mV of the power rails, (see Electrical Characteristics for
details).
When driving large capacitive loads, a series resistor should
be placed in series with the output. (Usually between 5Ω and
50Ω).
Each of the channels is updated on a continuous cycle, the
time for the new data to appear at a specific output will
depend on the exact timing relationship of the incoming data
to this cycle.
The best-case scenario is when the data has just been
captured and then passed on to the output stage
immediately; this can be as short as 48µs. In the worst-case
scenario, this will be 480µs when the data has just missed
the cycle.
When a large change in output voltage is required, the
change will occur in 2V steps, thus the requisite number of
timing cycles will be added to the overall update time. This
means that a large change of 16V can take between 3.8ms
LOAD
CLK
SDI
8
CHANNEL
MEMORY
FILTER
EIGHT
CONTROL IF
EL5225
SOURCES
VOLTAGE
and 4.2ms depending on the absolute timing relative to the
update cycle.
Output Stage and the Use of External Oscillator
Simplified output sample and hold amp stage for one
channel.
The output voltage is generated from the DAC, which is V
at the above circuit. The refreshed switches are controlled
by the internal or external oscillator signal. When the OSC
clock signal is low, the switch S
output V
hold cap CH is being charged. When the OSC clock signal is
high, the refreshed switch S
output voltage is maintained by CH. This refreshed process
EXT_OSC
1.3V
V
IN
OUT
= V
+
+
-
-
IN
and at the same time the sample and
REFERENCE HIGH
OUTA
OUTB
OUTH
OUTI
OUTJ
REFERENCE LOW
REFERENCE DECOUPLE
SDO
FIGURE 11.
S
1
1
and S
S
2
1
1.3V
and S
2
are opened and the
+
-
CH
2
are closed. The
OSC
March 11, 2004
V
OUT
FN7356.0
IN