ISL6523CBZ-T Intersil, ISL6523CBZ-T Datasheet - Page 14

• Manufacturer Part Number: ISL6523CBZ-T
• Description: IC CTRLR VRM8.5 PWM DUAL 28-SOIC
• Manufacturer: Intersil

Specifications of ISL6523CBZ-T

• Applications: Controller, Intel VRM8.5
• Voltage - Input: 5 ~ 15 V
• Number Of Outputs: 4
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -

The power dissipation in PWM2 converter is similar to
PWM1 except that the power losses of the lower device are
dissipated in the Schottky. The equations below describe an
approximation of this power loss distribution and assume
linear voltage-current switching transitions.
Linear Controllers Transistor Selection
The ISL6523 linear controllers are compatible with both NPN
bipolar as well as N-channel MOSFET transistors. The main
criteria for selection of pass transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is
Select a package and heatsink that maintains the junction
temperature below the maximum desired temperature with
the maximum expected ambient temperature.
When selecting bipolar NPN transistors for use with the
linear controllers, insure the current gain at the given
operating V
output load current when the base is fed with the minimum
driver output current.
In order to ensure the strict timing/level requirement of
OUT4, an NPN transistor is recommended for use as a pass
element on this output (Q5). An low gate threshold NMOS
could be used, but meeting the requirements would then
depend on the VCC bias being sufficiently high to allow
control of the MOSFET.
P
P
P
LINEAR
MOS
SCH
ISL6523
FIGURE 12. UPPER GATE DRIVE - DIRECT V
-
+
=
=
+12V
I
------------------------------------------------------------ -
I
----------------------------------------------------------- -
O
=
O
2
×
CE
I
O
×
V
r
×
f
is sufficiently large to provide the desired
DS ON
VCC
×
(
V
(
V
V
GND
(
V
IN
IN
IN
IN
UGATE
PHASE
LGATE
PGND
–
)
–
V
×
V
OUT
V
OUT
OUT
)
)
14
+
I
----------------------------------------------------
O
×
Q1
Q2
+5V OR LESS
V
IN
×
2
t
SW
CR1
NOTE:
V
×
NOTE:
V
GS
CC
GS
F
S
≈
≈
DRIVE
V
V
CC
CC
-5V
ISL6523