ISL6523CBZ Intersil, ISL6523CBZ Datasheet
ISL6523CBZ
Specifications of ISL6523CBZ
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ISL6523CBZ Summary of contents
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... TEMP. o PART NUMBER RANGE ( C) PACKAGE ISL6523CB SOIC ISL6523CBZ SOIC (See Note) (Pb-free) ISL6523EVAL1 Evaluation Board *Add “-T” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations ...
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VSEN3 VAUX 1.5V EA3 - DRIVE3 + x0.75 x0.75 + DRIVE4 - EA4 + VSEN4 1.8V - VCC DRIVE2 UGATE2 + - PHASE2 INHIBIT PWM GATE COMP2 CONTROL - + PWM2 - VSEN2 + EA2 UV2 - + x0.90 + ...
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IN V OUT2 +3. OUT3 +12V IN + OUT2 V OUT2 1.2V C OUT2 CR2 VTT POWERGOOD +3. OUT3 1.5V C OUT3 Q5 V OUT4 1.8V ...
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Absolute Maximum Ratings Supply Voltage .+15V CC ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued) PARAMETER UGATE1,2 Sink LGATE Source LGATE Sink PROTECTION OCSET1,2 Current Source Soft-Start Current POWER GOOD VSEN1 Upper Threshold (VSEN1/DACOUT) VSEN1 Under-Voltage (VSEN1/DACOUT) VSEN1 Hysteresis ...
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PGOOD (Pin 8) PGOOD is an open collector output used to indicate the status of the output voltages. This pin is pulled low when the synchronous regulator output is not within ±10% of the DACOUT reference voltage or when any ...
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The POR function initiates soft-start operation after all supply voltages exceed their POR thresholds. Soft-Start The 1.8V supply designed to power the chipset (OUT4), cannot lag the ATX 3.3V by more than 2V, at any time. To meet ...
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SS13UP UV3 OC LATCH S Q OC1 R COUNTER 4V R SS13 0.8V SS24 SS24UP POR 4V OV UV4 R OC2 LATCH FIGURE ...
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Determine I for I > I PEAK PEAK OUT(MAX) where ∆I is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. OVERCURRENT TRIP: V > V ...
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Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, radiate noise into ...
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Figure 10 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage ( regulated to the Reference voltage level. The OUT reference voltage level is the DAC output voltage (DACOUT) for PWM1. The error amplifier ...
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ESR of the output capacitor bank, as shown in the following equation: ESR OUT L = ------------------------------------------------ ( ) OUT MIN × π × 2 where L - minimum output inductor value at full output OUT(MIN) ...
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Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following ...
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OR LESS +12V VCC ISL6523 Q1 UGATE PHASE - LGATE Q2 + PGND GND FIGURE 12. UPPER GATE DRIVE - DIRECT V The power dissipation in PWM2 converter is similar to PWM1 except that the power losses of the ...
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... ISL6523 memory controller hub voltage (V and +12VDC. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note AN9925. Also see the Intersil web page (www.intersil.com) for the latest information. ), the AGP OUT1 ), and the OUT3 L1 1µ ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...