EL7586AILZ-T13 Intersil, EL7586AILZ-T13 Datasheet - Page 4
![IC POWER SUPPLY TFT-LCD 20-QFN](/photos/28/16/281691/20-vqfn_r_sml.jpg)
EL7586AILZ-T13
Manufacturer Part Number
EL7586AILZ-T13
Description
IC POWER SUPPLY TFT-LCD 20-QFN
Manufacturer
Intersil
Datasheet
1.EL7586AILZ-T13.pdf
(21 pages)
Specifications of EL7586AILZ-T13
Applications
Converter, TFT, LCD
Voltage - Input
3 ~ 5 V
Number Of Outputs
4
Voltage - Output
5.5 ~ 20 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Electrical Specifications
Pin Descriptions
FAULT DETECTION
t
OT
I
LOGIC ENABLE
V
V
I
I
PARAMETER
FAULT
PG
LOW
HIGH
HI
LO
PIN NAME
12, 13
9, 17
3, 4
10
14
15
16
18
19
20
11
1
2
5
6
7
8
Fault Time Out
Over-temperature Threshold
PG Pull-down Current
Logic High Threshold
Logic Low Threshold
Logic Low Bias Current
Logic High Bias Current
PIN NUMBER
LX1, LX2
SGND
PGND
DRVP
DRVN
CDLY
DELB
DRVL
VREF
CINT
VDD
FBP
FBN
FBB
FBL
EN
PG
DESCRIPTION
4
V
-40°C to 85°C, unless otherwise specified. (Continued)
DD
= 5V, V
A capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault
timeout time
Open drain output for gate drive of optional V
Drain of the internal N channel boost FET; for EL7586, pin 4 is not connected
Positive LDO base drive; open drain of an internal N channel FET
Positive LDO voltage feedback input pin; regulates to 1.2V nominal
Logic LDO base drive; open drain of an internal N channel FET
Logic LDO voltage feedback input pin; regulates to 1.2V nominal
Low noise signal ground
Negative LDO base drive; open drain of an internal P channel FET
Negative LDO voltage feedback input pin; regulates to 0.2V nominal
Power ground, connected to source of internal N channel boost FET
Bandgap voltage bypass, connect a 0.1µF to SGND
V
operation
Boost regulator voltage feedback input pin; regulates to 1.2V nominal
Enable pin, High = Enable; Low or floating = Disable
Positive supply
Push-pull gate drive of optional fault protection FET, when chip is disabled or when a fault has been
detected, this is high
BOOST
BOOST
integrator output, connect capacitor to SGND for PI mode or connect to V
= 11V, I
EL7586, EL7586A
C
VPG > 0.6V
VPG < 0.6V
at V
LOAD
DLY
EN
= 0.22µF
= 200mA, V
= 5V
CONDITION
ON
= 15V, V
DESCRIPTION
BOOST
OFF
delay FET
= -5V, V
LOGIC
MIN
2.3
12
= 2.5V, over temperature from
TYP
140
1.7
0.2
50
15
18
DD
MAX
0.8
for P mode
24
2
January 17, 2006
FN9210.2
UNIT
mA
ms
µA
µA
°C
µA
V
V