LT1943EFE#TR Linear Technology, LT1943EFE#TR Datasheet - Page 8

• Manufacturer Part Number: LT1943EFE#TR
• Description: IC REG SW QUAD TFT LCD 28-TSSOP
• Manufacturer: Linear Technology

Specifications of LT1943EFE#TR

• Applications: Converter, TFT, LCD
• Voltage - Input: 4.5 ~ 22 V
• Number Of Outputs: 4
• Voltage - Output: 1.25 ~ 40 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PI FU CTIO S
LT1943
SW3 (Pin 21): This is the collector of the internal NPN
bipolar power transistor for switching regulator 3. Mini-
mize metal trace area at this pin to keep EMI down.
BIAS (Pin 22): The BIAS pin is used to improve efficiency
when operating at higher input voltages. Connecting this
pin to the output of switching regulator 1 forces most of
the internal circuitry to draw its operating current from
V
are supplied by BIAS. Switches 2, 3 and 4 will not switch
until the BIAS pin reaches approximately 2.8V. BIAS must
be tied to V
PGOOD (Pin 23): Power Good Comparator Output. This is
the open collector output of the power good comparator
and can be used in conjunction with an external P-Channel
MOSFET to provide output disconnect for AV
in the 5V Input, Quad Output TFT-LCD Power Supply on
the last page of the data sheet. When switcher 2’s output
reaches approximately 90% of its programmed voltage,
PGOOD will be pulled to ground. This will pull down on the
gate of the MOSFET, connecting AV
8
LOGIC
U
rather than V
U
LOGIC
.
U
IN
. The drivers of switches 2, 3 and 4
DD
. A 100k pull-up
DD
as shown
resistor between the source and gate of the P-channel
MOSFET keeps it off when switcher 2’s output is low.
E3 (Pin 24): This is switching regulator 3’s output and the
emitter of the output disconnect PNP. Tie the output
capacitor and resistor divider here.
C
V
feedback pins reaching 1.125V to V
capacitor value can be set using the equation C = (20µA •
t
V
regulator 3. V
internal C
V
10% below normal voltage.
SW2 (Pins 27, 28): The SW2 pins are the collector of the
internal NPN bipolar power transistor for switching regu-
lator 2. These pins must be tied together. Minimize trace
area at these pins to keep EMI down.
DELAY
T
ON
ON
ON
(Pin 25): Timing Capacitor Pin. This is the input to the
is disabled if any of the four outputs are more than
(Pin 26): This is the delayed output for switching
timer and programs the time delay from all four
)/1.1V.
T
timer times out. Protection circuitry ensures
ON
reaches its programmed voltage after the
ON
turning on. The C
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T