LT1786FCS Linear Technology, LT1786FCS Datasheet - Page 7
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LT1786FCS
Manufacturer Part Number
LT1786FCS
Description
IC SW REG CCFL SMBUS PROG 16SOIC
Manufacturer
Linear Technology
Datasheet
1.LT1786FCS.pdf
(20 pages)
Specifications of LT1786FCS
Applications
Converter, CCFL
Voltage - Input
4.5 ~ 30 V
Number Of Outputs
1
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Voltage - Output
-
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Quantity
Price
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TYPICAL PERFORMANCE CHARACTERISTICS
PIN
CCFL PGND (Pin 1): This pin is the emitter of an internal
NPN power switch. CCFL switch current flows through
this pin and permits internal, switch-current sensing. The
regulator provides a separate analog ground and power
ground to isolate high current ground paths from low
current signal paths. Linear Technology recommends the
use of star-ground layout techniques.
I
programming circuit. This pin internally regulates to
465mV. The pin accepts a DC input current signal of 0 A
to 100 A full scale from the DAC. This input signal is
converted to a 0 A to 500 A source current at the CCFL V
pin. As input programming current increases, the regu-
lated lamp current increases.
DIO (Pin 3): This pin is the common connection between
the cathode and anode of two internal diodes. The remain-
ing terminals of the two diodes connect to ground. In a
grounded-lamp configuration, DIO connects to the low
voltage side of the lamp. Bidirectional lamp current flows
in the DIO pin and thus the diodes conduct alternately on
half cycles. Lamp current is controlled by monitoring one-
half of the average lamp current. The diode conducting on
negative half cycles has one-tenth of its current diverted to
the CCFL V
current provided by the lamp-current programmer circuit.
CCFL
U
(Pin 2): This pin is the input to the CCFL lamp current
FUNCTIONS
U
C
pin. This current nulls against the source
–0.2
–0.4
–0.6
–0.8
–1.0
1.0
0.8
0.6
0.4
0.2
0
DNL vs Code
0
U
16
W
CODE
U
32
48
1786 G27
64
C
A single capacitor on the CCFL V
loop compensation and an averaging function to the half-
wave-rectified sinusoidal lamp current. Therefore, input
programming current relates to one-half of average lamp
current. This scheme reduces the number of loop com-
pensation components and permits faster loop transient
response in comparison to previously published circuits.
If a floating lamp configuration is used, ground the DIO
pin.
CCFL V
programmer circuit and the input of the current compara-
tor for the CCFL regulator. Its uses include frequency
compensation, lamp-current averaging for grounded-lamp
circuits and current limiting. The voltage on the CCFL V
pin determines the current trip level for switch turn-off.
During normal operation this pin sits at a voltage between
0.95V (zero switch current) and 2.1V (maximum switch
current) with respect to analog ground (AGND). This pin
has a high impedance output and permits external voltage
clamping to adjust current limit. A single capacitor to
ground provides stable loop compensation. This simpli-
fied loop compensation method permits the CCFL regula-
tor to exhibit single-pole transient response behavior and
virtually eliminates transformer output overshoot.
–0.2
–0.4
–0.6
–0.8
–1.0
C
1.0
0.8
0.6
0.4
0.2
(Pin 4): This pin is the output of the lamp current
0
INL vs Code
0
16
CODE
32
C
48
pin provides both stable
1786 G28
64
LT1786F
7
C