ISL6227CAZ Intersil, ISL6227CAZ Datasheet - Page 15

• Manufacturer Part Number: ISL6227CAZ
• Description: IC CONTROLLER DDR, DDR2 28QSOP
• Manufacturer: Intersil
• Type: Pulse Width Modulator Controllerr

Specifications of ISL6227CAZ

• Applications: Controller, DDR, DDR2
• Voltage - Input: 5 ~ 28 V
• Number Of Outputs: 2
• Voltage - Output: 0.9 ~ 5.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• Current, Output: 10 mA
• Current, Supply: 1.8 mA
• Frequency, Oscillator: 300 kHz
• Package Type: QSOP-28
• Regulator Type: DC-DC
• Voltage, Input: 5 V
• Voltage, Output: 5.5 V
• Voltage, Supply: 5 V
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Voltage Program
The output voltage of either channel is set by a resistive divider
from the output to ground. The center point of the divider is
connected to the VSEN pin as shown in Figure 34. The
output voltage value is determined by Equation 3:
where 0.9V is the value of the internal reference. The VSEN
pin voltage is also used by the controller for the power good
function and to detect undervoltage and overvoltage
conditions.
Operation Mode Control
VOUTx pin programs the two channels of ISL6227 in two
different operational modes:
V
GND
Connects to output voltage
Connects to output voltage
1. If VOUTx is connected to ground, the channel will be put
2. If the VOUTx is connected to the output voltage, the
O
into a fixed switching frequency of 300kHz CCM, also
known as forced PWM mode regardless of load
conditions.
channel will operate in either fixed 300kHz PWM mode or
HYS mode, depending on the load conditions. It operates
in the PWM mode when the load current exceeds the
critical discontinuous conduction value, otherwise it will
operate in a HYS mode, as shown in the following table.
=
0.9V
--------------------------------------------- -
ISL6227
VOUT PIN
FIGURE 34. OUTPUT VOLTAGE PROGRAM
•
(
R2
R1
+
OCSET
UGATE
LGATE
R2
VOUT
VSEN
ISEN
)
Q2
R
Q1
CS
Any value
≤ I
>I
15
HYS1
HYS
INDUCTOR
CURRENT
V
R
IN
OC
L1
C1
Forced PWM
HYS
PWM
C
OPERATION
Z
MODE
V
R1
R2
O
(EQ. 3)
ISL6227
The two channels can be programmed to operate in different
modes depending on the VOUTx connection and the load
current. Once both channels operate in the PWM mode,
however, they will be synchronized to the 300kHz switching
clock. The 180° phase shift reduces the noise couplings
between the two channels and reduces the input current ripple.
The critical discontinuous conduction current value for the
PWM to HYS mode switch-over can be calculated by
Equation 4:
The HYS mode to PWM switch-over current I
determined by the activation time of the HYS mode
controller. It is affected by the ESR, the inductor value, the
input and output voltage.
The HYS mode control can improve converter efficiency with
reduced switching frequency. The efficiency is further
improved by the diode emulation scheme in discontinuous
conduction mode. The diode emulation scheme does not
allow the inductor sink current from the output capacitor,
thereby reducing the circulating energy. It is achieved by
sensing the free-wheeling current going through the
synchronous MOSFET through Phase node voltage polarity
change after the upper MOSFET is turned off. Before the
current reverses direction, the lower MOSFET gate pulses
are terminated.
The PWM-HYS and HYS-PWM switch-over is provided
automatically by the mode control circuit, which constantly
monitors the inductor current through phase voltage polarity,
and alters the way the gate driver pulse signal is generated.
Mode Transition
For a buck regulator, if the load current is higher than critical
value I
in the free-wheeling period is always negative, and vice
versa. The mode control circuit monitors the phase node
voltage in the off-period. The polarity of this voltage is used
as the criteria for whether the load current is greater than the
critical value, and thus determines whether the converter will
operate in PWM or HYS mode.
To prevent chatter between operating modes, the circuit
looks for eight sequentially matching polarity signals before it
decides to perform a mode change. The algorithm is true for
both CCM-HYS and HYS-CCM transitions.
In the HYS mode, the PWM comparator and the error
amplifier, that provided control in the CCM mode, are put in a
clamped stage and the hysteretic comparator is activated. A
change is also made to the gate logic. The synchronous
MOSFET is controlled in diode emulation fashion, hence the
current in the synchronous MOSFET will be kept in one
direction only. Figures 35 and 36 illustrate the mode change
by counting eight switching cycles.
I
HYS
=
HYS1
----------------------------------------------------
2 F
(
•
V
, the voltage drop on the synchronous MOSFET
IN
SW
–
V
•
O
L
O
) V
•
•
V
O
IN
HYS1
is
May 4, 2009
(EQ. 4)
FN9094.7