ISL6566CRZ-TR5184 Intersil, ISL6566CRZ-TR5184 Datasheet - Page 18

• Manufacturer Part Number: ISL6566CRZ-TR5184
• Description: IC CTRLR PWM 3PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6566CRZ-TR5184

• Applications: Controller, Intel VRM9, VRM10, and AMD Hammer Applications
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.84 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL6566CRZ-TR5184; ISL6566CRZ-TR5184TR

When each of these conditions is true, the controller
immediately begins the soft-start sequence.
2. The voltage on ENLL must be above 0.66V. The ENLL
3. The driver bias voltage applied at the PVCC pins must
4. The VID code must not be 111111 or 111110 in VRM10
FIGURE 11. POWER SEQUENCING USING THRESHOLD-
input allows for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6566 in shutdown until the
voltage at ENLL rises above 0.66V. The enable
comparator has 60mV of hysteresis to prevent bounce.
reach the internal power-on reset (POR) rising threshold.
In order for the ISL6566 to begin operation, PVCC1 is the
only pin that is required to have a voltage applied that
exceeds POR. However, for 2 or 3-phase operation
PVCC2 and PVCC3 must also exceed the POR
threshold. Hysteresis between the rising and falling
thresholds assure that once enabled, the ISL6566 will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see Electrical Specifications).
mode or 11111 in AMD Hammer or VRM9 modes. These
codes signal the controller that no load is present. The
controller will enter shut-down mode after receiving either
of these codes and will execute soft-start upon receiving
any other code. These codes can be used to enable or
disable the controller but it is not recommended. After
receiving one of these codes, the controller executes a
2-cycle delay before changing the overvoltage trip level to
the shut-down level and disabling PWM. Overvoltage
shutdown cannot be reset using one of these codes.
CIRCUIT
FAULT LOGIC
SOFT-START
POR
AND
ISL6566 INTERNAL CIRCUIT
SENSITIVE ENABLE (ENLL) FUNCTION
ENABLE
COMPARATOR
18
+
-
0.66V
EXTERNAL CIRCUIT
VCC
PVCC1
ENLL
10.7kΩ
1.40kΩ
+12V
ISL6566
SOFT-START
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. Following a delay of 16 PHASE clock cycles
between enabling the chip and the start of the ramp, the
output voltage progresses at a fixed rate of 12.5mV per each
16 PHASE clock cycles.
Thus, the soft-start period (not including the 16 PHASE clock
cycle delay) up to a given voltage, V
approximated by the following equation
where V
switching frequency.
The ISL6566 also has the ability to start up into a pre-
charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level.
T
SS
GND>
GND>
FIGURE 12. SOFT-START WAVEFORMS FOR ISL6566-BASED
=
V
---------------------------------
OUTPUT PRECHARGED
DAC
DAC
BELOW DAC LEVEL
f
S
OUTPUT PRECHARGED
⋅
is the DAC-set VID voltage, and f
MULTI-PHASE CONVERTER
1280
ABOVE DAC LEVEL
T1
T2
T3
DAC
, can be
V
OUT
ENLL (5V/DIV)
S
is the
(0.5V/DIV)
March 9, 2006
(EQ. 13)
FN9178.4