LP2996MR/NOPB National Semiconductor, LP2996MR/NOPB Datasheet - Page 15

IC DDR TERMINATION REG 8PSOP

LP2996MR/NOPB

Manufacturer Part Number
LP2996MR/NOPB
Description
IC DDR TERMINATION REG 8PSOP
Manufacturer
National Semiconductor
Datasheet

Specifications of LP2996MR/NOPB

Applications
Converter, DDR
Voltage - Input
2.2 ~ 5.5 V
Number Of Outputs
1
Operating Temperature
0°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-PSOP
Polarity
Positive
Input Voltage Max
5.5 V
Output Voltage
1.159 V, 1.259 V, 1.359 V
Output Type
Fixed
Output Current
1.5 A
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Reference Voltage
1.358 V
For Use With
LP2996MREVAL - BOARD EVALUATION LP2996MR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Output
-
Lead Free Status / Rohs Status
 Details
Other names
*LP2996MR
*LP2996MR/NOPB
LP2996MR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
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Part Number:
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Manufacturer:
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Quantity:
115
Part Number:
LP2996MR/NOPB
Manufacturer:
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Quantity:
20 000
PCB Layout Considerations
1.
2.
3.
4.
The input capacitor for the power rail should be placed
as close as possible to the PVIN pin.
V
at the point where regulation is required. For
motherboard applications an ideal location would be at
the center of the termination bus.
V
either the DIMM or the Chipset. This provides the most
accurate point for creating the reference voltage.
For improved thermal performance excessive top side
copper should be used to dissipate heat from the
SENSE
DDQ
can be connected remotely to the V
should be connected to the V
TT
termination bus
DDQ
rail input at
15
5.
6.
package. Numerous vias from the ground connection to
the internal ground plane will help. Additionally these can
be located underneath the package if manufacturing
standards permit.
Care should be taken when routing the V
avoid noise pickup from switching I/O signals. A 0.1uF
ceramic capacitor located close to the
used to filter any unwanted high frequency signal. This
can be an issue especially if long
V
ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the
V
REF
REF
should be bypassed with a 0.01 µF or 0.1 µF
pin.
SENSE
SENSE
traces are used.
SENSE
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can also be
trace to

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