SG3525ADWR2 ON Semiconductor, SG3525ADWR2 Datasheet - Page 7

• Manufacturer Part Number: SG3525ADWR2
• Description: IC PWM SMPS CONTROLLER 16-SOIC
• Manufacturer: ON Semiconductor

Specifications of SG3525ADWR2

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 400kHz
• Duty Cycle: 49%
• Voltage - Supply: 8 V ~ 35 V
• Buck: No
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Frequency-max: 400kHz
• Topology: Half-Bridge, Push-Pull
• Output Current: 400 mA
• Switching Frequency: 400 KHz
• Duty Cycle (max): 49 %
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Fall Time: 50 ns
• Mounting Style: SMD/SMT
• Rise Time: 100 ns
• Synchronous Pin: Yes
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The low source impedance of the output drivers provides
rapid charging of power FET input capacitance while
minimizing external components.
For single−ended supplies, the driver outputs are grounded.
The V
source transistors on alternate oscillator cycles.
+
Figure 10. Single−Ended Supply
V
Figure 12. Driving Power FETS
+
supply
C
V
supply
terminal is switched to ground by the totem−pole
SG3525A
GND
V
C
13
12
R1
A
B
R1
SG3525A
11
14
GND
Q1
V
C
12
R2
13
Q1
Q2
A
B
To Output Filter
14
11
Clock
5.0k
Q1
F/F
T1
Q4
10k
V
Q2
ref
Figure 9. Output Circuit
Q5
PWM
(1/2 Circuit Shown)
http://onsemi.com
10k
Q3
V
SG3525A
CC
Q6
7
in SG3527A
Q8
Q6 Omitted
Q7
Q9
+V
In conventional push−pull bipolar designs, forward base drive is
controlled by R1−R3. Rapid turn−off times for the power devices
are achieved with speed−up capacitors C1 and C2.
Low power transformers can be driven directly by the SG3525A.
Automatic reset occurs during deadtime, when both ends of the
primary winding are switched to ground.
supply
+V
5.0k
SG3525A
2.0k
Figure 13. Driving Transformers in a
supply
Q10
Figure 11. Push−Pull Configuration
GND
Q11
V
C
SG3525A
13
13
12
A
B
GND
Half−Bridge Configuration
Output
V
V
C
C
11, 14
11
14
13
12
R1
A
B
11
14
T1
C1
C2
R3
R2
Q1
Q2
R2
R1
Q1
Q2
T2
T1
C1
C2