UC3843BVDG ON Semiconductor, UC3843BVDG Datasheet - Page 11
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UC3843BVDG
Manufacturer Part Number
UC3843BVDG
Description
IC CTRLR CURRENT MODE HP 14SOIC
Manufacturer
ON Semiconductor
Datasheet
1.UC3842BDR2G.pdf
(21 pages)
Specifications of UC3843BVDG
Pwm Type
Current Mode
Number Of Outputs
1
Frequency - Max
275kHz
Duty Cycle
96%
Voltage - Supply
8.2 V ~ 25 V
Buck
No
Boost
Yes
Flyback
Yes
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
Yes
Operating Temperature
-40°C ~ 105°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Frequency-max
275kHz
Duty Cycle (max)
96 %
Output Current
1000 mA
Mounting Style
SMD/SMT
Switching Frequency
500 KHz
Maximum Operating Temperature
+ 105 C
Fall Time
50 ns
Minimum Operating Temperature
- 40 C
Rise Time
50 ns
Synchronous Pin
No
Topology
Boost, Flyback, Forward
Number Of Pwm Outputs
1
On/off Pin
No
Adjustable Output
No
Switching Freq
500KHz
Operating Supply Voltage (max)
30V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
14
Package Type
SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
UC3843BVDGOS
DI
Inductor
Current
Control Voltage
f +
C
Control Voltage
R
R
6
5
2
A
B
(R A ) 2R B )C
8
1.44
Figure 20. Continuous Current Waveforms
Figure 22. External Duty Cycle Clamp and
1
5.0k
5.0k
5.0k
t
t
4
0
m
MC1455
Multi−Unit Synchronization
1
R
S
Oscillator Period
Dl ) Dl m 2
D (max) +
Q
4
DI
m
Oscillator Period
1
m 1
R A ) 2R B
m
t
3
7
2
1
R B
m
3
(B)
(A)
8(14)
4(7)
2(3)
1(1)
t
Dl ) Dl m 2
2
t
m
5
To Additional
UCX84XBs
2
EA
m 1
R
R
m 2
m 1
+
Osc
Bias
http://onsemi.com
2R
Inductor
Current
R
t
3
t
6
5(9)
11
R
R
2
1
V
8(14)
Clamp
4(7)
2(3)
1(1)
Figure 23. Adjustable Reduction of Clamp Level
External
≈
The diode clamp is required if the Sync amplitude is large enough to cause the bottom
side of C
Sync
Input
R 2
R 1
R
R
Figure 21. External Clock Synchronization
EA
T
1.67
) 1
to go more than 300 mV below ground.
+
Osc
Bias
1.0 mA
0.01
+ 0.33x10
2R
R
C
-
+
-3
R
47
T
V
5(9)
T
Clamp
1.0V
R 1 ) R 2
R 1 R 2
5.0V Ref
8(14)
V
4(7)
2(3)
1(1)
ref
Comp/Latch
S
R
Where: 0 ≤ V
I pk(max) [
Q
EA
R
R
Clamp
+
V Clamp
Osc
7(12)
R S
+
-
Bias
≤ 1.0 V
V
CC
7(11)
6(10)
5(8)
3(5)
2R
R
5(9)
V
Q1
R
in
S