ISL6721AV Intersil, ISL6721AV Datasheet - Page 17

• Manufacturer Part Number: ISL6721AV
• Description: IC CTRLR PWM SGL-ENDED 16-TSSOP
• Manufacturer: Intersil

Specifications of ISL6721AV

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 100%
• Voltage - Supply: 9 V ~ 18 V
• Buck: Yes
• Boost: Yes
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 16-TSSOP
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

minimum V
minimum ESR.
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the bandwidth
to about f
limited due to the low GBWP of the LM431-based Error
Amplifier and the opto-coupler. A bandwidth of approximately
5kHz was selected.
For the EA compensation, the first pole is placed at the
origin by default (C
zero is placed below the crossover frequency, f
around 1/3 f
ESR zero or at one half of the switching frequency. The
midband gain is then adjusted to obtain the desired
crossover frequency. If the phase margin is not adequate,
the crossover frequency may have to be reduced.
Using this technique to determine the compensation, the
following values for the EA components were selected.
R
R
C
C
A Bode plot of the closed loop system at low line, max load
appears in Figures 9A and 9B.
17
20
13
14
= R
= open
= 100nF
= 100pF
18
sw
= R
IN
-100
/4. For this example, the bandwidth will be further
co
200
150
100
-50
-10
-20
-30
-40
-50
50
50
40
30
20
10
, maximum load, maximum C
0
0
10k
. The second pole is placed at the lower of the
10k
15
FIGURE 9B. PHASE MARGIN
= 1kΩ
14
FIGURE 9A. GAIN
is an integrating capacitor). The first
100k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
17
1M
1M
10M
10M
OUT
, and
co
, usually
100M
100M
ISL6721
Regulation Performance
Waveforms
Typical waveforms can be found in Figures 10 through 12.
Figure 10 shows the steady state operation of the sawtooth
oscillator waveform at RTCT (Trace 2), the SYNC output
pulse (Trace 1), and the GATE output to the converter FET
(Trace 3). Figure 11 shows the converter behavior while
operating in an overcurrent fault condition. Trace 1 is the
soft-start voltage, which increases from 0V to 4.5V, at which
point the OC fault function is enabled. The OC condition is
detected and the soft-start capacitor is discharged to the
I
OUT
0.39
0.88
1.38
1.87
2.39
2.89
3.37
0.39
0.88
1.38
1.87
2.39
2.89
0.39
0.88
1.38
1.87
2.39
0.39
0.88
1.38
1.87
0.39
0.88
1.38
0.39
0.88
0.39
(A), 3.3V
TABLE 1. OUTPUT LOAD REGULATION, V
0
0
0
0
0
0
0
I
OUT
0.030
0.030
0.030
0.030
0.030
0.030
0.030
0030
0.52
0.52
0.52
0.52
0.52
0.52
0.52
1.05
1.05
1.05
1.05
1.05
1.05
1.55
1.55
1.55
1.55
1.55
2.07
2.07
2.07
2.07
2.62
2.62
2.62
3.14
3.14
(A), 1.8V V
OUT
3.351
3.281
3.251
3.223
3.204
3.185
3.168
3.153
3.471
3.283
3.254
3.233
3.218
3.203
3.191
3.619
3.290
3.254
3.235
3.220
3.207
3.699
3.306
3.260
3.239
3.224
3.762
3.329
3.270
3.245
3.819
3.355
3.282
3.869
3.383
(V), 3.3V V
IN
OUT
= 48V
1.825
1.956
1.988
2.014
2.029
2.057
2.084
2.103
1.497
1.800
1.836
1.848
1.855
1.859
1.862
1.347
1.730
1.785
1.805
1.814
1.820
1.265
1.682
1.750
1.776
1.789
1.201
1.645
1.722
1.752
1.142
1.612
1.697
1.091
1.581
March 5, 2008
(V), 1.8V
FN9110.6