ISL6549CA Intersil, ISL6549CA Datasheet
![IC CTRLR PWM DUAL REG 16-QSOP](/photos/6/86/68635/20-16-qsop_sml.jpg)
ISL6549CA
Specifications of ISL6549CA
Available stocks
Related parts for ISL6549CA
ISL6549CA Summary of contents
Page 1
... ISL6549CB ISL6549CB ISL6549CBZ (Note) 6549CBZ ISL6549CR ISL6549CR ISL6549CRZ (Note) 6549CRZ ISL6549CA ISL6549CA ISL6549CAZ (Note) 6549CAZ ISL6549CAZA (Note) 6549CAZ ISL6549IBZ (Note) 6549IBZ ISL6549IRZ (Note) 6549IRZ ISL6549IAZ (Note) 6549IAZ ISL6549LOW-EVAL1 Evaluation Board 1-5A ISL6549HI-EVAL1 Evaluation Board up to 20A Add “-T” suffix for tape and reel. ...
Page 2
Pinouts ISL6549 (SOIC) TOP VIEW BOOT 14 1 UGATE FS_DIS 2 13 PHASE 12 COMP 3 PGND LGATE 5 10 LDO_DR PVCC5 LDO_FB 6 9 VCC5 GND 7 8 VCC12 Block Diagram VOLTAGE REFERENCE LDO_FB LDO_DR EA2 ...
Page 3
Simplified Power System Diagram +V IN1 +12V +V IN2 V OUT2 + Typical Application Schematic +V IN1 +12V C +V IN2 + C VIN2 Q3 V OUT2 + C OUT2 3 ISL6549 LINEAR Q3 CONTROLLER CONTROLLER ISL6549 VCC12 PVCC5 BP ...
Page 4
Absolute Maximum Ratings VCC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to ...
Page 5
Recommended Operating Conditions, unless otherwise noted. VCC12 = 12V Electrical Specifications Temperature = 0 to +70°C (typical = +25°C) for Commercial; Temperature = - 85°C (typical = +25°C) for Industrial. Refer to Block Diagram, Simplified Power System Diagram, ...
Page 6
Functional Pin Description VCC12 This is the power supply pin for the IC; it sources the internal 5V regulator used for the gate drivers. Provide a local decoupling capacitor to GND. The voltage at this pin is monitored for Power-On ...
Page 7
Description Operation Overview The ISL6549 monitors and precisely controls two output voltage levels. Refer to the “Block Diagram” on page 2, “Simplified Power System Diagram” on page 3, and “Typical Application Schematic” on page 3. The controller is intended for ...
Page 8
GND> GND> FIGURE 2. EXPANDED VIEW: VOLTAGE RAMP AND TIME A few clock cycles are used for initialization to insure that soft- start begins near zero volts. The ramps are the same, whether triggered by releasing FS_DIS or by ...
Page 9
If either V voltage is not present at startup, that will cause a INx UV shutdown and restart cycle; similarly, if either V removed after start-up, a shutdown ...
Page 10
For most situations, no external compensation is required for the linear output. See “Linear Controller Feedback Compensation” on page 12. For both outputs, the selection of 1% resistors may not be able to get the exact ratio desired for any ...
Page 11
COMP - FB + E/A VREF OSCILLATOR V OSC PWM CIRCUIT UGATE HALF-BRIDGE DRIVE PHASE LGATE ISL6549 EXTERNAL CIRCUIT FIGURE 10. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN Use the following guidelines for locating the poles and zeros of ...
Page 12
⎛ ⎞ R2 ------- - 20 log ⎝ ⎠ LOG FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN A stable control loop has ...
Page 13
An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of ...
Page 14
FET is particularly slow in these parameters, there is a greater chance that shoot-through current will occur. As referenced in the “Block Diagram” on page 2, the UGATE signal is referenced to PHASE signal. The deadtime comparator also looks at ...
Page 15
... C 5 GND FB FS_DIS R 7 LDO_DR LDO_FB KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA CONNECTION TO GROUND PLANE FIGURE 13. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS References Applications Note: AN1201 Visit us on the internet: www.intersil.com , C , and IN1 C IN1 OUT V OUT1 ...
Page 16
... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation ...
Page 17
Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...
Page 18
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...