HIP6311CB-T Intersil, HIP6311CB-T Datasheet - Page 13

• Manufacturer Part Number: HIP6311CB-T
• Description: IC CTRLR PWM MULTIPHASE 20-SOIC
• Manufacturer: Intersil

Specifications of HIP6311CB-T

• Pwm Type: Controller
• Number Of Outputs: 4
• Frequency - Max: 305kHz
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Frequency-max: 305kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Duty Cycle: -

average current per phase. Neglecting secondary effects,
the sampled current (I
current (I
I
V
Where: I
Example: Using the previously given conditions, and
For I
Then I
As discussed previously, the voltage drop across each Q2
transistor at the point in time when current is sampled is
r
PHASE node, is applied through the R
HIP6311 ISEN pin. This pin is held at virtual ground, so the
current into ISEN is:
I
R
Example: From the previous conditions,
where I
I
r
Then: R
I
Short circuit I
Channel Frequency Oscillator
The channel oscillator frequency is set by placing a resistor,
R
showing the relationship between frequency, F
resistor R
to place this resistor next to the pin. If this pin is also used to
disable the converter, it is also important to locate the pull-
down device next to this pin.
SAMPLE
SENSE
SAMPLE
CURRENT TRIP
DSON
DS(ON)
IN
Isen
T
, to ground from the FS/DIS pin. Figure 10 is a curve
)
LT
n = 4
SAMPLE
(Q2) x I
LT
ISEN
(Q2)
LT
= 100A,
= I
= I
= I
T
LT
. To avoid pickup by the FS/DIS pin, it is important
n = the number of channels
) by:
SAMPLE
SAMPLE
LT
LT
= total load current
/ n + (V
SAMPLE
= 25.49A
= 100A,
= 25.49A,
= 4mΩ
= 2.04K and
= 165%
= 165A.
x r
x r
IN
SAMPLE
. The voltage at Q2’s drain, the
DS(ON)
DS(ON)
V
CORE
13
) can be related to the load
(Q2) / R
(Q2) / 50µA
- 3V
CORE
ISEN
ISEN
2
) / (6L x F
.
resistor to the
SW
, and
SW
x
HIP6311
HIP6311
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device over-voltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying channel current. During the
turnoff, current stops flowing in the upper MOSFET and is
picked up by the lower MOSFET. Any inductance in the
switched current path generates a large voltage spike during
the switching interval. Careful component selection, tight
layout of the critical components, and short, wide circuit
traces minimize the magnitude of voltage spikes. Contact
Intersil for evaluation board drawings of the component
placement and printed circuit board.
There are two sets of critical components in a DC-DC
converter using a HIP6311 controller and a HIP6601 gate
driver. The power components are the most critical because
they switch large amounts of energy. Next are small signal
components that connect to sensitive nodes or supply critical
bypassing current and signal coupling.
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors, C
and the power switches. Locate the output inductors and
output capacitors between the MOSFETs and the load.
Locate the gate driver close to the MOSFETs.
1,000
500
200
100
50
20
10
5
2
1
10
FIGURE 10. RESISTANCE R
20
CHANNEL OSCILLATOR FREQUENCY, F
50
100
200
500 1,000
T
vs FREQUENCY
2,000
SW
December 27, 2004
(kHz)
5,000 10,000
FN4817.3
IN
,