HIP6021CB-T Intersil, HIP6021CB-T Datasheet - Page 8

• Manufacturer Part Number: HIP6021CB-T
• Description: IC PWM TRPL PWR CONTROL 28-SOIC
• Manufacturer: Intersil

Specifications of HIP6021CB-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 4
• Frequency - Max: 215kHz
• Duty Cycle: 100%
• Voltage - Supply: 10.8 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: Yes
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 215kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Applications Guidelines for a procedure to determine the
soft-start interval.
Fault Protection
All four outputs are monitored and protected against extreme
overload. A sustained overload on any output or an over-
voltage on V
drives the FAULT/RT pin to VCC.
Figure 4 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
latch. A sequence of three over-current fault signals also
sets the fault latch. The over-current latch is set dependent
upon the states of the over-current (OC), linear under-
voltage (LUV) and the soft-start signals. A window
comparator monitors the SS pin and indicates when C
LUV
OC1
OV
0V
0V
0V
SS
0.15V
FIGURE 4. FAULT LOGIC - SIMPLIFIED SCHEMATIC
4V
VOLTAGES
(0.5V/DIV)
OUTPUT
T0
+
-
+
-
T1
OUT1
SOFT-START
FIGURE 3. SOFT-START INTERVAL
PGOOD
(1V/DIV)
CURRENT
UP
LATCH
OVER-
output (VSEN1) disables all outputs and
S
R
Q
T2
POR
TIME
8
R
COUNTER
T3
V
OUT1
INHIBIT
V
V
V
OUT2
OUT4
OUT3
LATCH
FAULT
(DAC = 2.5V)
S
R
( = 3.3V)
( = 1.8V)
( = 1.5V)
Q
T4
VCC
SS
FAULT
is
HIP6021
fully charged to 4V (UP signal). An under-voltage on either
linear output (VSEN2, VSEN3, or VSEN4) is ignored until
after the soft-start interval (T4 in Figure 3). This allows
V
up. Cycling the bias input voltage (+12V
then on) resets the counter and the fault latch.
Over-Voltage Protection
During operation, a short on the upper MOSFET of the PWM
regulator (Q1) causes V
exceeds the over-voltage threshold of 115% of DACOUT, the
over-voltage comparator trips to set the fault latch and turns
Q2 on. This blows the input fuse and reduces V
fault latch raises the FAULT/RT pin to VCC.
A separate over-voltage circuit provides protection during the
initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2 is driven on.
Over-Current Protection
All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s
on-resistance, r
against shorted output. All linear controllers monitor their
respective VSEN pins for under-voltage events to protect
against excessive currents.
Figure 5 illustrates the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
current increases through the inductor (L
the OVER-CURRENT comparator trips when the voltage
across Q1 (i
ROCSET. This inhibits all outputs, discharges the soft-start
capacitor (C
the counter. C
cycle with the error amplifiers clamped by soft-start. With
OUT1 still overloaded, the inductor current increases to trip
the over-current comparator. Again, this inhibits all outputs,
but the soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start
cycle repeats at T3 and trips the over-current comparator.
The SS pin voltage increases to 4V at T4 and the counter
increments to 3. This sets the fault latch to disable the
converter. The fault is reported on the FAULT/RT pin.
The linear controllers operate in the same way as the PWM
in response to over-current faults. The differentiating factor
for the linear controllers is that they monitor the VSEN pins
for under-voltage events. Should excessive currents cause
the voltage at the VSEN pins to fall below the linear under-
voltage threshold, the LUV signal sets the over-current
latch if C
the C
above the under-voltage threshold during normal operation.
Cycling the bias input power off then on resets the counter
and the fault latch.
OUT2
SS
, V
SS
charge interval allows the linear outputs to build
OUT3
is fully charged. Blanking the LUV signal during
D
SS
SS
• r
) with a 10mA current sink, and increments
, and V
DS(ON)
DS(ON)
recharges at T2 and initiates a soft-start
OUT4
to monitor the current for protection
) exceeds the level programmed by
OUT1
to increase without fault at start-
to increase. When the output
IN
OUT1
on the VCC pin off
). At time T1,
OUT1
. The