MIC2184BM Micrel Inc, MIC2184BM Datasheet - Page 10

• Manufacturer Part Number: MIC2184BM
• Description: IC CTRLR PWM BUCK LV 16-SOIC
• Manufacturer: Micrel Inc

Specifications of MIC2184BM

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 440kHz
• Duty Cycle: 100%
• Voltage - Supply: 2.9 V ~ 14 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 440kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MIC2184
The line voltage turn on trip point is:
where:
comparator reference, typically 1.5V
The input voltage hysteresis is equal to:
where:
typically 140mV.
The MIC2184 will be disabled when the input voltage drops
back down to:
Either of 2 UVLO conditions will pull the soft start capacitor
low.
The internal bias circuit generates an internal 1.245V band-
gap reference voltage for the voltage error amplifier and a 3V
V
13) should be decoupled with a 0.1µf capacitor placed close
to the pin. The V
capacitor. The capacitor must be placed close to the V
The other end of the capacitor must be connected directly to
the ground plane.
MOSFET Gate Drive
The MIC2184 is designed to drive a high side P-channel
MOSFET. The source pin of the P-channel MOSFET is
connected to the input of the power supply. It is turned on
when OUTP pulls the gate of the MOSFET low. The advan-
tage of using a P-channel MOSFET is that it does not require
a bootstrap circuit to boost the gate voltage higher than the
input, as would be required for an N-channel MOSFET.
The V
drive pin, OUTP. V
M9999-042205
DD
• When the V
• When the enable pin drops below the its enable
voltage for the internal control circuitry. The V
V
V
V
V
(V
V
V
IN
V
undervoltage lockout level.
threshold
THRESHOLD
HYST
INPUT_OFF
INPUT_ENABLE
INPUT ENABLE
INPUT HYST
INPUT_HYST
THRESHOLD
P pin (pin 16) supplies the drive voltage to the gate
R1
R2
V
IN
_
_
is the internal comparator hysteresis level,
EN/UVLO
(7)
DD
Figure 3. UVLO Circuitry
Typical
=
1.5V
=
DD
pin must be decoupled with a 1µF ceramic
is the voltage level of the internal
IN
V
is the hysteresis at the input voltage
– V
=
P pin is usually connected to the input
HYST
– V
voltage drops below its
V
THRESHOLD
HYST
INPUT_HYST
Hysteresis
×
(typical)
140mV
R
)
1
×
R
MIC2184
+
R
2
R
1
R
×
+
2
2
R
R
Circuitry
=
1
2
Bias
R
+
2
R
2
REF
pin (pin
DD
pin.
10
supply. The V
same potential.
MOSFET Selection
The P-channel MOSFET must have a V
equal to or lower than the input voltage when used in a buck
converter topology. There is a limit to the maximum gate
charge the MIC2184 will drive. Higher gate charge MOSFET
will slow down the turn-on and turn-off time of the MOSFET.
Slower transition times will cause higher power dissipation in
the MOSFET due to higher switching transition losses.
The MOSFET gate charge is also limited by power dissipation
in the MIC2184. The power dissipated by the gate drive
circuitry is calculated below:
where: Qgate is the total gate charge of both the N and P-
channel MOSFETs.
The graph in Figure 4 shows the total gate charge that can be
driven by the MIC2184 over the input voltage range, for
different values of switching frequency.
Oscillator & Sync
The internal oscillator is free running and requires no external
components. The f/2 pin allows the user to select from two
switching frequencies. A low level set the oscillator frequency
to 400kHz and a high level set the oscillator frequency to
200kHz. The maximum duty cycle for both frequencies is
100%. This is another advantage of using a P-channel
MOSFET for the high-side drive; it can continuously turned
on.
A frequency foldback mode is enabled if the voltage on the
feedback pin (pin 6) is less than 0.3V. In frequency foldback,
the oscillator frequency is reduced by approximately a factor
of 4. Frequency foldback is used to limit the energy delivered
to the output during a short circuit fault condition.
The SYNC input (pin 11) lets the MIC2184 synchronize with
an external clock signal. The rising edge of the sync signal
generates a reset signal in the oscillator, which turns off the
low side gate drive output. The high side drive then turns on,
restarting the switching cycle. The sync signal is inhibited
when the controller operates in frequency foldback. The sync
signal frequency must be greater than the maximum speci-
Figure 4. MIC2184 Frequency vs Max. Gate Charge
P
f
V
S
GATE_DRIVE
IN
is the switching frequency
P is the gate drive voltage at the V
IN
200x10
180x10
160x10
140x10
120x10
100x10
P pin and CSH pin must be connected to the
80x10
60x10
40x10
20x10
0x10
=
-9
-9
-9
-9
-9
-9
-9
-9
-9
-9
0
3
Q
500kHz
GATE
5
Max. Gate Charge
INPUT VOLTAGE (V)
Frequency vs.
7
600kHz
×
9
V P f
IN
11 13 15 17
×
S
200kHz
300kHz
400kHz
GS
threshold voltage
IN
P pin
Micrel, Inc.
April 2005