IR3094MPBF International Rectifier, IR3094MPBF Datasheet - Page 20

• Manufacturer Part Number: IR3094MPBF
• Description: IC 3 PHASE PWM CONTROL 48MLPQ
• Manufacturer: International Rectifier

Specifications of IR3094MPBF

• Pwm Type: Voltage Mode
• Number Of Outputs: 3
• Frequency - Max: 540kHz
• Duty Cycle: 100%
• Voltage - Supply: 8 V ~ 16 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 150°C
• Package / Case: 48-MLPQ
• Frequency-max: 540kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IR3094PBF
Master-Slave Current Share Loop
Current sharing between phases of the converter is achieved by a Master-Slave current share loop topology. The
output of the Phase 1 Current Sense Amplifier sets the reference for the Share Adjust Error Amplifiers. Each Share
Adjust Error Amplifier adjusts the duty cycle of its respective PWM Ramp and to force its input error to zero
compared to the master Phase 1, resulting in accurate current sharing.
The maximum and minimum duty cycle adjust range of Ramps 2 & 3 compared to Ramp1 has been limited to a
minimum of 0.5x and a maximum of 2.0x typical (see Figure 3.). The crossover frequency of the current share loop
can be programmed with a capacitor at the SCOMPX pin so that the share loop does not interact with the output
voltage loop.
The SCOMPX capacitor is driven by a trans-conductance stage capable of sourcing and sinking 22uA. The duty
cycle of Ramps 2 & 3 inversely tracks the voltage on their SCOMPX pin; if V(SCOMP2) increases, Ramp2’s slope
will increase and the effective duty cycle will decrease resulting in a reduction in Phase 2’s output current. Due to
the limited 22uA source current, an SCOMPX pre-conditon circuit has been included to pre-condition V(SCOMPX)
so that the duty cycle of Ramps 2 & 3 are equal to Ramp1 prior to any GATEHX high pulses.
The pre-condition
circuit can source/sink 360uA. The SYNC LATCH (see Figure 1) releases the pre-condition circuit once FB reaches
78% of VREF.
Set BIASOUT voltage
BIASOUT pin provides a 150mA open-loop regulated voltage for GATE drive bias. The voltage is set by SETBIAS
through an external resistor Rset connecting between SETBIAS pin and ground. Bias current I
is a function of
SETBIAS
ROSC. Rset is chosen by equation (15). V
in the equation is the forward voltage drop across the Bootstrap diode.
FD

V
V
BIASOUT
FD
R
(15)
SET
I
SETBIAS
Compensation of the Current Share Loop
The crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop
in order to eliminate the interaction between the two loops. A 22nF capacitor from SCOMP to LGND is good for
most of the applications. If necessary have a resistor in series with the Csc to make the current loop a little bit
faster.
Compensation of Voltage Loop
The selection of compensation types depends on the output capacitors used in the converter. For the applications
using Electrolytic, Polymer or AL-Polymer capacitors and running at lower frequency, type II compensation shown in
Figure 9(a) is usually enough. While for the applications using only ceramic capacitors and running at higher
frequency, type III compensation shown in Figure 9(b) is preferred.
For applications without voltage droop, the compensation is the same as for the regular voltage mode control. For
converter using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero frequency, type
III compensation is required as shown in Figure 9(b) with R
and C
removed.
DRP
DRP
Page 20 of 29
09/26/05