CS51022ADBR2G ON Semiconductor, CS51022ADBR2G Datasheet - Page 7

• Manufacturer Part Number: CS51022ADBR2G
• Description: IC CTRLR PWM ENH SYNC 16-TSSOP
• Manufacturer: ON Semiconductor

Specifications of CS51022ADBR2G

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 83%
• Voltage - Supply: 8.2 V ~ 20 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: Yes
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Frequency-max: 1MHz
• Duty Cycle (max): 83 %
• Output Current: 1000 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 1000 KHz
• Operating Supply Voltage: - 0.3 V to + 20 V
• Maximum Operating Temperature: + 150 C
• Fall Time: 15 ns
• Rise Time: 60 ns
• Synchronous Pin: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Powering the IC
PGND pins provide high speed power drive for the external
power switch. V
portion of the IC. The internal logic monitors the supply
voltage, V
output is held low. The CS51021A/2A/3A/4A requires only
75 mA of startup current.
Voltage Feedback
compared with the internal 2.5 V reference. The error
amplifier output minus one diode drop is divided by 3 and
connected to the negative input of the PWM comparator.
The positive input of the PWM comparator is connected to
the modified current sense signal. The oscillator turns the
external power switch on at the beginning of each cycle.
When current sense ramp voltage exceeds the reference side
of PWM comparator, the output stage latches off. It is turned
on again at the beginning of the next oscillator cycle.
The IC has two supply and two ground pins. V
The output voltage is monitored via the V
0 V
0 V
0 V
0 V
0 V
V
0 V
IN
V
SLOPE
T
200 ns
CH
CC
4.3 V
IS + 0.1 SLOPE
. During abnormal operating conditions, the
IS
Figure 3. Typical Waveforms
T
THEORY OF OPERATION
DIS
CC
and LGND pins power the control
CS51021A, CS51022A, CS51023A, CS51024A
Blanking
55 ns
FB
PWM COMP
CIRCUIT DESCRIPTION
pin and is
SYNC
R
SLOP
E
IS
V
GATE
V
T
COMP
DS
C
http://onsemi.com
C
T
and
7
Current Sense and Protection
CS51021A/2A/3A/4A has leading edge blanking circuitry
that ignores the first 55 ns of each switching period.
Blanking is disabled when V
minimum on−time of the controller does not have an
additional 55 ns of delay time during fault conditions. For
the remaining portion of the switching period, the current
sense signal, combined with a fraction of the slope
compensation voltage, is applied to the positive input of the
PWM comparator where it is compared with the divided by
three error amplifier output voltage. The pulse−by−pulse
overcurrent protection threshold is set by the voltage at the
I
appears at the non−inverting input of the PWM comparator,
limiting its dynamic range according to the following
formula:
where
and
the slope of the current sense signal will become much
steeper than during normal operation. Due to loop
propagation delay, the sensed signal will overshoot the
pulse−by−pulse threshold eventually reaching the second
overcurrent protection threshold which is 1.33 times higher
than the first threshold and is described by the following
equation:
capacitor C
repeating for as long as the fault condition persists.
Soft Start
discharged and the output voltage is low, the voltage across
the Soft Start capacitor (V
internal current source of 55 mA charges C
error amplifier output voltage is clamped by the SS Clamp.
When the Soft Start capacitor voltage exceeds the error
amplifier output voltage, the feedback loop takes over the
duty cycle control. The Soft Start time can be estimated with
the following formula:
between 0.25 V and 4.7 V.
SET
The current is monitored at the I
During extreme overcurrent or short circuit conditions,
Exceeding the second threshold will reset the Soft Start
During power up, when the output filter capacitor is
The Soft Start voltage, V
Overcurrent Threshold + 0.8
pin. This voltage is passed through the I
V I(SENSE) is voltage at the I SENSE pin.
V SLOPE is voltage at the SLOPE pin.
2nd Threshold + 1.33
SS
and reinitiate the Soft Start sequence,
t SS + 9
SS
FB
) controls the duty cycle. An
10
SS
) 0.1 V ) 0.1 V SLOPE
is less than 2.0 V so that the
4
, charges and discharges
C SS
V I(SENSE)
V I(SET)
SS
SENSE
. The maximum
SET
Clamp and
pin. The