NCP1562BDR2G ON Semiconductor, NCP1562BDR2G Datasheet - Page 19
![IC CLAMP/RESET PWM CTLR 16-SOIC](/photos/5/67/56711/488-16-soic_sml.jpg)
NCP1562BDR2G
Manufacturer Part Number
NCP1562BDR2G
Description
IC CLAMP/RESET PWM CTLR 16-SOIC
Manufacturer
ON Semiconductor
Datasheet
1.NCP1562ADBR2G.pdf
(26 pages)
Specifications of NCP1562BDR2G
Pwm Type
Voltage Mode
Number Of Outputs
2
Frequency - Max
1MHz
Duty Cycle
85%
Voltage - Supply
23.2 V ~ 100 V
Buck
No
Boost
Yes
Flyback
Yes
Inverting
Yes
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-40°C ~ 125°C
Package / Case
16-SOIC (3.9mm Width)
Frequency-max
1MHz
Topology
Flyback, Forward, Half-Bridge
Output Voltage
20 V
Output Current
2000 mA, 1000 mA
Switching Frequency
1000 KHz
Duty Cycle (max)
85 %
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Fall Time
10 ns
Mounting Style
SMD/SMT
Rise Time
26 ns
Synchronous Pin
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
NCP1562BDR2G
NCP1562BDR2GOSTR
NCP1562BDR2GOSTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NCP1562BDR2G
Manufacturer:
ON Semiconductor
Quantity:
4 000
Part Number:
NCP1562BDR2G
Manufacturer:
ON/安森美
Quantity:
20 000
(patent pending). This architecture allows both the UV and
OV levels to be set independently. Both the UV and OV
detectors have a 100 mV hysteresis.
shown in Figure 42.
V
UV turn threshold. Once the UVOV voltage exceeds 2.5 V,
an internal current source (I
the UVOV pin. This will clamp the UVOV voltage at 2.5 V
while the current across R1 is less than I
input voltage continues to increase, the 50 mA source will
be overridden and the voltage at the UVOV pin will
increase. An OV condition exists if the UVOV voltage
exceeds V
relationship between UVOV and V
voltage is solely determined by the ratio of R1 and R2. The
input voltage at which the converter turns ON is given by
UV
The line voltage is sampled using a resistor divider as
A UV condition exists if the UVOV voltage is below
While the internal current source is disabled, the UVOV
, typically 2.0 V. The ratio of R1 and R2 determines the
Figure 43. UVOV Detectors Typical Waveforms
V
V
R1
R2
UVOV
UVCOMP
V
in
Figure 42. Line UVOV Detectors
OV
, typically 3.0 V. Figure 43 shows the
C
UVOV
UVOV
Time
V
OVCOMP
offset(UVOV)
I
offset(UVOV)
+
- -
+
- -
+
- -
3.0 V
2.0 V
2.5 V
+
+
+
in
- -
- -
- -
.
OV Comparator
UV Comparator
) sinks 50 mA into
offset(UVOV)
V
V
OVCOMP
UVCOMP
http://onsemi.com
. If the
19
Equation 1. Once the internal current source is enabled, the
absolute value of R1 together with the ratio of R1 and R2
determine the turn OFF threshold as shown in Equation 2.
manufacturing to obtain 3% accuracy allowing a tighter
power stage design.
V
soft- - start sequence commences. If a UV or OV fault is
detected afterwards, the converter enters a soft- - stop mode.
UVOV pin to GND to prevent oscillation of the UVOV pin
and filter line transients.
Line Feedforward
limit the maximum volt- - second product. It is the line
voltage times the ON time. This limit prevent saturation of
the transformer in forward and flyback topologies. Another
advantage of feedforward is a controller frequency gain
independent of line voltage. A constant gain facilitates
frequency compensation of the converter.
proportional to V
error signal solely controls the duty cycle while the input
voltage is fixed. If the line voltage changes, the FF Ramp
slope changes and duty cycle is immediately adjusted instead
of waiting for the change to propagate around the feedback
loop and be reflected back on the error signal.
from the input line as shown in Figure 44. The divider is
selected such that the FF Ramp reaches 3.0 V in the desired
maximum ON time. The FF Ramp terminates by
effectively grounding C
This can be triggered by the FF Ramp reaching 3.0 V, or
any other condition that limits the duty cycle.
during standby mode to prevent the FF pin from charging
up to V
V in(OV) = V OV
AUX
The undervoltage threshold is trimmed during
Once the line voltage is within the operating range, and
A small capacitor is required (>1000 pF) from the
The NCP1562 incorporates line feedforward (FF) to
Feedforward is implemented by generating a ramp
The FF Ramp is generated with an R- - C (R
The FF pin is effectively grounded during power or
FF Reset
Figure 44. Feed Forward Ramp Generation
reaches V
in
To PWM and VS
.
Comparators
V in(UV) = V UV ×
(R 1 + R 2 )
in
AUX(on)
and comparing it to the error signal. The
R 2
I
FF(D)
FF
, the outputs are enabled and a
during the converter OFF time.
+ (I offset(UVOV) × R1)
R
C
FF
(R 1 + R 2 )
FF
FF
V
R 2
in
I
RFF
t
FF
on
T
C
FF
) divider
0 V
(eq. 1)
3 V
(eq. 2)