ISL9506HRZ-T Intersil, ISL9506HRZ-T Datasheet
ISL9506HRZ-T
Specifications of ISL9506HRZ-T
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ISL9506HRZ-T Summary of contents
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... MARKING (°C) ISL9506HRZ ISL9506 HRZ -10 to +100 40 Ld 6x6 QFN L40.6x6 ISL9506HRZ-T ISL9506 HRZ -10 to +100 40 Ld 6x6 QFN *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach ...
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Functional Pin Description PMON 2 RBIAS 3 4 VRHOT# 5 NTC GND PAD (BOTTOM) 6 SOFT 7 OCSET COMP (Pin ...
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PWM2 (Pin 26) PWM output for Channel 2. For ISL9506, LP low will make this output tri-state. When PWM2 is pulled to 5V VDD, PWM2 will be disabled and allow other channels to operate. PWM1 (Pin 27) PWM output for ...
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... ISL9506 Thermal Information Thermal Resistance (Notes QFN Package Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = -10°C to +100°C, unless otherwise noted. Parameters with MIN and/or A SYMBOL TEST CONDITIONS I VR_EN = 3.3V ...
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Electrical Specifications Operating Conditions: VDD = 5V, T MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER ISEN Imbalance Voltage Input Bias Current SOFT CURRENT Soft-start Current ...
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Electrical Specifications Operating Conditions: VDD = 5V, T MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER PGD_N OUTPUT LEVELS PGD_N High Output Voltage PGD_N Low Output ...
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Typical Operating Performance 100 8. 12. 0.1 1.0 I (A) OUT FIGURE 5. DIODE EMULATION MODE EFFICIENCY, 3 PHASE, DCM OPERATION LOW, VSEL = 0.75V ...
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Typical Operating Performance 1. 8.0V 1. 12.6V 1.42 IN 1.41 1.40 1. 19.0V IN 1.38 1.37 1. (A) OUT FIGURE 11. DIODE EMULATION MODE DROOP IMPEDANCE, 2 PHASE, DCM OPERATION, ...
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Typical Operating Performance FIGURE 17. 3 PHASE CURRENT BALANCE, FULL LOAD = 50A V OUT COMP PIN FIGURE 19. TRANSIENT LOAD RESPONSE, 40A LOAD STEP @ 200A/µs, 3 PHASE FIGURE 21. TRANSIENT LOAD 3 PHASE OPERATION, ZOOM OF RISING EDGE ...
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Typical Operating Performance VSEL MSB V OUT FIGURE 23. VSEL MSB BIT CHANGE FROM 1.4375V TO 0.65V SHOWING 9mV/µs SLEW RATE, DE_EN = 0, DE_ENN = 1 V OUT DE_ENN AND LP FIGURE 25. C4 ENTRY AND EXIT SLEW RATES ...
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Typical Operating Performance I PHASE V OUT PGOOD FIGURE 29. WOCP - SHORT CIRCUIT PROTECTION LP PGD_N V OUT PHASE 2 FIGURE 31. ISL9506 PHASE ADDING AND DROPPING IN DIODE EMULATION MODE, LOAD CURRENT = 4.35A 11 ISL9506 (Continued) PWM ...
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Typical Operating Performance PHASE 1 CURRENT PHASE 2 CURRENT FIGURE 33. ISL9506, INDUCTOR CURRENT WAVEFORM WITH PHASE ADDING AND DROPPING IN CCM OR NOMINAL MODE 1.8 1.6 19V, 1.15V, 40A 1.4 1.2 19V, 1.15V, 30A 1.0 0.8 19V, 1.15V, 20A ...
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Simplified Application Circuit for DCR Current Sensing Figure 39 shows a simplified application circuit for the ISL9506 converter with inductor DCR current sensing. The ISL6208 MOSFET gate driver has a force-continuous-conduction-mode (FCCM) input, that when disabled, allows the regulator to ...
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Simplified Application Circuit for Resistive Current Sensing Figure 40 shows a simplified application circuit for the ISL9506 converter with external resistor current sensing. A capacitor is added in parallel with RL in order to improve the stability margin of the ...
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Functional Block Diagram RBIAS VSEL0 VSEL1 VSEL2 DAC VSEL3 DACOUT VSEL4 IBAL VSEL5 VSEL6 MODE CONTROL FCCM VO VR_EN MODE LP SOFT CONTROL DE_EN DE_ENN NUMBER OF 10µA PHASES GAIN SELECT) OCSET VSUM + DROOP DFB - DROOP + 1 ...
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... It can be programmed for 1 channel operation. With ISL6208 gate driver capable of diode emulation, the ISL9506 provides optimum efficiency in both heavy and light load conditions. 3 ISL9506 uses Intersil patented R (Robust Ripple 3 Regulator®) modulator. The R ® modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings ...
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TABLE 1. VOLTAGE SELECTION TABLE (Continued) VSEL5 VSEL4 VSEL3 VSEL2 VSEL1 VSEL0 VSEL6=0 VSEL6 ...
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... For fastest recovery from Diode Emulation to Nominal mode, DE_EN LOW achieves higher dV/dt. 3 Intersil's R intrinsically has voltage-feed-forward. The output voltage is insensitive to a fast slew input voltage change. Refer to Figure 15 in the “Typical Operating Performance” ...
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TABLE 3. THE FAULT PROTECTION AND RESET OPERATION OF ISL9506 FAULT DURATION PRIOR TO PROTECTION Overcurrent 120µs Way-Overcurrent (2.5 X <2µs OC) Overvoltage 1.7V Immediately Overvoltage +200mV 1ms Undervoltage -300mV 1ms Phase-Current Unbalance 1ms Over-Temperature Immediately Protection The ISL9506 provides ...
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The 7Ω impedance is associated with the layout and packaging resistance of PMON pin inside the IC. Compared to the ...
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As mentioned in the ““Theory of Operation” on page 16 section of this data sheet, PGD_N is logic level high at start- up. When the output voltage reaches 90% of start voltage, a counter is enabled, it counts 13 switching ...
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Equation 7: 1.24V 1.20V --------------- - – --------------- - = 2.96k 54μA 60μA Therefore, proper NTC thermistor has to be chosen such that 2.96k resistor change will be corresponding to required ...
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µ ...
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DCR = 0.0012Ω typical, Rdrp1 = 1kΩ and the attenuation gain (G1) = 0.57, Rdrp2 is then: × ⎛ ⎞ 3 0.0021 × Rdrp2 = ----------------------------------- - 1 – 8.21kΩ ⎝ ⎠ × 0.0012 0.57 Rdrp2 is selected ...
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The compensation design has to ensure the output impedance of the converter be lower than this desired value. There is a mathematical calculation file available to the user. The power stage parameters such as L and Cs are needed ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 6.00 6 PIN 1 INDEX AREA 0.15 (4X) TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 27 ...