ISL6244HRZ Intersil, ISL6244HRZ Datasheet - Page 15

• Manufacturer Part Number: ISL6244HRZ
• Description: IC CTRLR PWM 2-4-PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6244HRZ

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 4
• Frequency - Max: 4MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -10°C ~ 100°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 4MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Second, the ISL6244 features an enable input (EN) for
power sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6244 in shutdown until the voltage at EN rises above
1.23V. The enable comparator has about 90mV of hysteresis
to prevent bounce. It is important that the driver ICs reach
their POR level before the ISL6244 becomes enabled. The
schematic in Figure 20 demonstrates sequencing the
ISL6244 with the ISL620X family of Intersil MOSFET drivers
which require 5V bias.
The 11111 VID code is reserved as a signal to the controller
that no load is present. The controller will enter shutdown
mode after receiving this code and will start up upon
receiving any other code. This code is not intended as a
means of enabling the controller when a load is present.
To enable the controller, VCC must be greater than the POR
threshold; the voltage on EN must be greater than 1.23V;
and VID cannot be equal to 11111. Once these conditions
are true, the controller immediately initiates a soft-start
sequence.
Soft-Start
The soft-start time, t
that increments with every pulse of the phase clock. For
example, a converter switching at 250kHz per phase has a
soft-start time of
During the soft-start interval, the soft-start voltage, V
increases linearly from zero to 140% of the programmed
DAC voltage. At the same time a current source, I
decreasing from 160µA down to zero. These signals are
connected as shown in Figure 21 (I
connected to FB depending on the particular application).
T
FIGURE 20. POWER SEQUENCING USING THRESHOLD-
SS
=
2048
------------ -
f
SW
OV LATCH
CIRCUIT
SIGNAL
POR
ISL6244 INTERNAL CIRCUIT
=
SENSITIVE ENABLE (EN) FUNCTION
8.3ms
SS
, is determined by an 11-bit counter
ENABLE
COMPARATOR
1.23V (±2%)
15
+
-
OUT
EXTERNAL CIRCUIT
VCC
EN
may or may not be
+5V
3.64kΩ
1.40kΩ
+5V
RAMP
RAMP
(EQ. 10)
, is
,
ISL6244
The ideal diodes in Figure 21 assure that the controller tries
to regulate its output to the lower of either the reference
voltage or V
across R
seen until V
produces a delay after the ISL6244 enables before the
output voltage starts moving. For example, if VID = 1.5V,
R
expressed using Equation 11.
Following the delay, the soft start ramps linearly until V
reaches VID. For the system described above, this first
linear ramp will continue for approximately
The final portion of the soft-start sequence is the time
remaining after V
zero. This is also characterized by a slight change in the slope
of the output voltage ramp which, for the current example,
exists for a time of
This behavior is seen in the example in Figure 22 of a
converter switching at 500kHz. For this converter, R
set to 2.67kΩ leading to T
t
t
t
t
RAMP1
DELAY
RAMP1
RAMP2
R
FIGURE 21. RAMP CURRENT AND VOLTAGE FOR
FB
FB
= 1kΩ and T
EXTERNAL CIRCUIT
=
= 2.23ms, and t
=
=
=
=
R
FB
C
-------------------------------------------------- -
1
T
---------- -
5.27ms
T
2.34ms
1.4
RAMP
of (R
RAMP
+
SS
SS
REGULATING SOFT-START SLOPE
AND DURATION
---------------------------------------- -
R
C
–
–
FB
C
1.4 VID
RAMP
t
FB
t
SS
T
RAMP1
DELAY
. Since I
160
is greater than the R
SS
COMP
VDIFF
(
IOUT
x 160µA), the first PWM pulse will not be
= 8.3ms, the delay time can be
FB
×
reaches VID and before I
10
RAMP2
)
–
–
RAMP
t
DELAY
SS
6
ISL6244 INTERNAL CIRCUIT
=
I
= 4.0ms, t
AVG
560µs
= 1.17ms.
creates an initial offset
I
RAMP
ERROR AMPLIFIER
FB
V
DELAY
IDEAL DIODES
RAMP
I
RAMP
+
-
December 28, 2004
RAMP
= 700ns,
REFERENCE
VOLTAGE
offset. This
V
COMP
(EQ. 13)
(EQ. 11)
(EQ. 12)
FB
gets to
FN9106.3
RAMP
is