ISL6524ACBZ Intersil, ISL6524ACBZ Datasheet - Page 11

• Manufacturer Part Number: ISL6524ACBZ
• Description: IC CTRLR VRM8.5 PWM TRPL 28-SOIC
• Manufacturer: Intersil

Specifications of ISL6524ACBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 4
• Frequency - Max: 215kHz
• Duty Cycle: 100%
• Voltage - Supply: 10.8 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 215kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the PHASE node, but do not
unnecessarily oversize this particular island. Since the
PHASE node is subject to very high dV/dt voltages, the stray
capacitor formed between these island and the surrounding
circuitry will tend to couple switching noise. Use the
remaining printed circuit layers for small signal wiring. The
wiring traces from the control IC to the MOSFET gate and
source should be sized to carry 2A peak currents.
PWM1 Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a voltage-mode controller requiring external
compensation.
Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
reference voltage level is the DAC output voltage (DACOUT)
for the PWM. The error amplifier output (V
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V
The PWM wave is smoothed by the output filter (L
+5V
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND
OUT
V
OUT3
IN
+3.3V
+3.3V
V
OUT2
KEY
) is regulated to the Reference voltage level. The
IN
IN
C
C
L
SS24,13
OUT3
IN
C
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE
C
IN
OUT2
ISLANDS
Q3
Q4
+12V
DRIVE2
SS13
SS24
DRIVE3
VCC
ISL6524A
C
VCC
PGND
11
GND
OCSET
DRIVE4
PHASE
LGATE
UGATE
IN
C
Q2
E/A
OCSET
at the PHASE node.
Q5
) is compared with
Q1
R
L
C
OCSET
CR1
OUT
C
OUT4
O
OUT1
and C
V
V
OUT4
OUT1
O
).
The modulator transfer function is the small-signal transfer
function of V
Gain, given by V
a double pole break frequency at F
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6524A) and the impedance networks Z
and Z
closed loop transfer function with high 0dB crossing frequency
(f
difference between the closed loop phase at f
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 11. Use these guidelines for locating the poles
and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
0dB
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
F
∆
LC
V
) and adequate phase margin. Phase margin is the
FB
OSC
=
. The goal of the compensation network is to provide a
--------------------------------------- -
2π
ST
ND
ST
ND
V
×
OUT
E/A
OSC
COMPENSATION DESIGN
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero
L
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
1
ERROR
AMP
IN
DETAILED COMPENSATION COMPONENTS
O
/V
ISL6524A
/V
×
E/A
C
COMP
OSC
PWM
Z
+
-
COMP
O
. This function is dominated by a DC
FB
-
+
C1
, and shaped by the output filter, with
REFERENCE
C2
DACOUT
-
+
R2
DRIVER
DRIVER
Z
F
IN
ESR
LC
FB
=
and a zero at F
Z
V
FB
---------------------------------------- -
2π
IN
PHASE
(PARASITIC)
C3
×
0dB
ESR
Z
R1
L
IN
1
O
R3
and 180
×
ESR
C
V
C
O
OUT
April 8, 2005
O
ESR
LC
FN9064.1
V
IN
o
)
OUT
.
.