ISL6535IBZ Intersil, ISL6535IBZ Datasheet - Page 12

• Manufacturer Part Number: ISL6535IBZ
• Description: IC CTRLR SYNC BUCK PWM 14-SOIC
• Manufacturer: Intersil

Specifications of ISL6535IBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 100%
• Voltage - Supply: 10.8 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for
use with the ISL6535. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from +12V. The boot capacitor, C
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of +12V
less the boot diode drop (V
turns on. A MOSFET can only be used for Q
MOSFETs absolute gate-to-source voltage rating exceeds
the maximum voltage applied to +12V. For Q
MOSFET can be used if its absolute gate-to-source voltage
rating also exceeds the maximum voltage applied to +12V.
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
+
-
ISL6535
+12V
+
D
GND
V
BOOT
PHASE
D
BOOT
UGATE
PVCC
LGATE
PGND
-
+12V
D
C
) when the lower MOSFET, Q
12
BOOT
Q1
Q2
+1.2V TO +12V
D2
1
NOTE:
V
2
NOTE:
V
G-S
, a logic-level
if the
G-S
≈ V
≈ PVCC
BOOT
CC
- V
D
2
ISL6535
Figure 10 shows the upper gate drive supplied by a direct
connection to +12V. This option should only be used in
converter systems where the main input voltage is +5 VDC
or less. The peak upper gate-to-source voltage is
approximately +12V less the input supply. For +5V main
power and +12V DC for the bias, the gate-to-source voltage
of Q
and a logic-level MOSFET can be used for Q
gate-to-source voltage rating exceeds the maximum voltage
applied to PVCC. This method reduces the number of
required external components, but does not provide for
immunity to phase node ringing during turn on and may
result in lower system efficiency.
FIGURE 10. UPPER GATE DRIVE - DIRECT V
Schottky Selection
Rectifier D
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the
diode and let the body diode of the lower MOSFET clamp
the negative inductor swing, but efficiency could slightly
decrease as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
+
-
1
ISL6535
+12V
is 7V. A logic-level MOSFET is a good choice for Q
2
is a clamp that catches the negative inductor
GND
BOOT
UGATE
LGATE
PGND
PVCC
+12V
Q1
Q2
+5V OR LESS
D2
CC
V
NOTE:
2
NOTE:
V
G-S
DRIVE OPTION
G-S
if its absolute
≈
≈
V
PVCC
CC
May 5, 2008
FN9255.1
- 5V
1