ISL6341BCRZ-T Intersil, ISL6341BCRZ-T Datasheet - Page 10

• Manufacturer Part Number: ISL6341BCRZ-T
• Description: IC CTRLR SYNC BUCK PWM 10-TDFN
• Manufacturer: Intersil

Specifications of ISL6341BCRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 660kHz
• Duty Cycle: 75%
• Voltage - Supply: 4.5 V ~ 14.4 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 10-TDFN Exposed Pad
• Frequency-max: 660kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4ms during the sampling; that could discharge a pre-biased
output. Therefore, to avoid that case, but still come close to
disabling OCP, a resistor (>60kΩ) is recommended.
Note that conditions during power-up may look different than
normal operation. For example, during power-up in a 12V
system, the IC starts operation just above 4V; if the supply
ramp is slow, the soft-start ramp might be over well before
12V is reached. So with lower gate drive voltages, the
r
effectively lowering the OCP trip. In addition, the ripple
current will likely be different at lower input voltage.
Another factor is the digital nature of the soft-start ramp. On
each discrete voltage step, there is in effect a small load
transient and a current spike to charge the output capacitors.
The height of the current spike is not controlled; it is affected
by the step size of the output, the value of the output
capacitors, as well as the IC error amp compensation. So it
is possible to trip the overcurrent with in-rush current, in
addition to the normal load and ripple considerations.
OCP is always enabled during soft-start, so there is
protection starting up into a shorted load.
Undervoltage Protection
The output is protected against undervoltage conditions by
monitoring the VOS pin. An external resistor divider (similar
ratio to the one on the FB pin) makes the voltage equal the
0.8V internal reference under normal operation. If the output
goes too low (25% below 0.8V = 0.6V nominal on VOS), the
output will latch off, with UGATE and LGATE both forced low.
This requires toggling V
(toggling COMP/EN will NOT restart it). The UV protection is
not enabled until the end of the soft-start ramp (as shown in
Figure 2).
Figure 7 shows a case where V
down to the 75% point; both gate drivers stop switching, and
the V
load, at a rate determine by the conditions, and the output
components.
The ISL6341C version does not have UVP; it relies on the
OCP for shorted loads. The PGOOD UV comparator is
separate, and is still active.
DS(ON)
OUT
of the MOSFETs will be higher during power-up,
is pulled low by the disturbance, as well as the
CC
(power-down and up) to restart
10
OUT
(and thus VOS) is pulled
ISL6341, ISL6341A, ISL6341B, ISL6341C
Overvoltage Protection
The output is protected against overvoltage conditions by
monitoring the VOS pin, similar to undervoltage. If the output
goes too high (25% above 0.8V = 1.0V nominal on VOS), the
output will latch off. As shown in Figure 8, UGATE will be
forced low, but LGATE will be forced high (to try to pull-down
the output) until the output drops to 1/2 of the normal voltage
(50% of 0.8V = 0.4V nominal on VOS). The LGATE will then
shut off, but will keep turning back on whenever the output
goes too high again.
Overvoltage latch-off requires toggling V
up) to restart (toggling COMP/EN will NOT restart it). The OV
protection is not enabled until the rising V
exceeded. The OV protection is active during soft-start at the
fixed 25% above the final expected voltage. The OVP is not
gated off by tripping OCP (but the UVP is gated off if OCP
trips first).
If the VOS pin is disconnected, a small bias current on-chip
will force an overvoltage condition.
125%
GND>
GND>
GND>
GND>
GND>
GND>
75%
50%
LGATE (12V/DIV)
UGATE (24V/DIV)
UGATE (24V/DIV)
V
LGATE (12V/DIV)
FIGURE 7. UNDERVOLTAGE PROTECTION
OUT
FIGURE 8. OVERVOLTAGE PROTECTION
(0.5V/DIV)
V
OUT
(0.25V/DIV)
CC
CC
(power-down and
POR trip point is
December 2, 2008
FN6538.2