ISL6439AIBZ Intersil, ISL6439AIBZ Datasheet - Page 10

• Manufacturer Part Number: ISL6439AIBZ
• Description: IC CTRLR PWM SYNC BUCK 14-SOIC
• Manufacturer: Intersil

Specifications of ISL6439AIBZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 650kHz
• Duty Cycle: 100%
• Voltage - Supply: 3.3 V ~ 5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Frequency-max: 650kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ΔV
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6439) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. The expressions in Equation 5 relate the
compensation network’s poles, zeros and gain to the
components (R
these guidelines for locating the poles and zeros of the
compensation network:
F
ΔV
1. Pick gain (R
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin - repeat if necessary.
2. Place first zero below filter’s double pole (~75% F
LC
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
OSC
=
FB
----------------------------------------- -
2π x
. The goal of the compensation network is to provide
OSC
0dB
COMPARATOR
L
1
COMPENSATION DESIGN
O
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
V
ISL6439
1
) and adequate phase margin. Phase margin
x C
E/A
2
, R
PWM
/R
Z
+
O
-
2
1
FB
-
+
COMP
) for desired converter bandwidth.
, R
C
REFERENCE
2
REFERENCE
3
, C
C
+
1
-
1
DRIVER
DRIVER
R
10
F
, C
Z
2
ESR
IN
2
, and C
OSC
=
FB
Z
------------------------------------------ -
2π x ESR x C
FB
.
PHASE
(PARASITIC)
V
C
3
IN
3
) in Figure 5. Use
IN
L
Z
R
1
IN
O
1
) divided by the
R
ESR
C
3
O
V
OUT
O
LC
ISL6439, ISL6439A
0dB
V
(EQ. 4)
).
OUT
and
IN
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Charge Pump Capacitor Selection
A capacitor across pins CT1 and CT2 is required to create
the proper bias voltage for the ISL6439 when operating the
IC from 3.3V. Selecting the proper capacitance value is
important so that the bias current draw and the current
required by the MOSFET gates do not overburden the
F
F
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
Z1
Z2
100
-20
-40
-60
80
60
40
20
0
and Z
=
=
--------------------------------- -
2π
------------------------------------------------------ -
2π x R
10
MODULATOR
20
×
IN
log
GAIN
R
(
1
to provide a stable, high bandwidth (BW) overall
⎛
⎝
2
100
R2
------- -
R1
1
×
F
1
+
Z1
C
⎞
⎠
R
2
3
) x C
F
1K
LC
F
FREQUENCY (Hz)
3
Z2
F
ESR
10K
F
P1
F
F
P1
P2
P2
100K
F
=
=
with the capabilities of
P2
-------------------------------------------------------- -
2π x R
----------------------------------- -
2π x R
1M
ERROR AMP GAIN
1
2
3
COMPENSATION
20
OPEN LOOP
x
x C
1
LOOP GAIN
November 5, 2008
⎛
⎜
⎝
log
10M
C
--------------------- -
C
3
GAIN
1
1
⎛
⎜
⎝
--------------- -
V
x C
+
V
FN9057.5
(EQ. 5)
OSC
C
IN
2
2
⎞
⎟
⎠
⎞
⎟
⎠