LT1619ES8 Linear Technology, LT1619ES8 Datasheet - Page 11

• Manufacturer Part Number: LT1619ES8
• Description: IC PWM CNTRLR CURRENT-MODE 8SOIC
• Manufacturer: Linear Technology

Specifications of LT1619ES8

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 500kHz
• Duty Cycle: 92%
• Voltage - Supply: 1.9 V ~ 18 V
• Buck: No
• Boost: Yes
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: Yes
• Isolated: Yes
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 500kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Here the input voltage ripple is filtered with R3, R4 and C1
so as to prevent the input ripple from falsely tripping the
LT1619 synchronization circuit. It is recommended that:
Implementation of Hysteretic UVLO
with External Synchronization
The UVLO circuit shown in Figure 10 operates down to
0.9V supply voltage. Algebraically the UVLO trip points
are:
Figure 10. Addition of Hysteresis UVLO While Synchronizing the
LT1619. Component Values Shown are for the Upper and the
Lower V
is Disabled by Pulling the V
Down the LT1619. If Not Synchronized, the Collector of Q2 Can
Be Tied to the S/S Pin and the Diode D1 Can Be Eliminated
UVLO Hysteresis V
V
and
V
and
INH
INL
V
IN
8.2V
IN
R
51k
51k
+
–
R5
R6
2
Trip Points of 10V and 8.4V. In UVLO, the Gate Drive
R
4
V
Z
5
R
||
5
1
3
V
30k
R
1
R
R
||
R8
BE
7
5
3
R C
4 1
Q1
2N2222
U
1
R
51k
R7
9
510k
V
R
INH
BE
R9
C
6
V
R
Pin Low. Disabling the Clock Shuts
U
Z
||
5
–
Q2
2N2222
R
f
R
OSC
6
V
7
V
R
INL
BAT85
||
BE
5
CLK
D1
V
V
R
IN
IN
7
UPPER TRIP POINT = 10V
LOWER TRIP POINT = 8.4V
R
W
–
5
R
R
1
2
3
4
R
||
5
5
5
R
S/S
FB
V
GND
||
C
|| || R
6
LT1619
R
R
R
||
R
7
5
7
SENSE
7
R
6
GATE
DRV
1619 F10
U
V
7
IN
R
R
R
9
9
9
8
7
6
5
R
9
V
Z
The collector votage of Q2 is made about 1.4V at the V
lower trip voltage. This is necessary to prevent the UVLO
circuit from interfering with the feedback amplifier in the
LT1619.
Trickle Current Start from High Voltage Supplies
The low shutdown and idle mode quiescent supply cur-
rents of the LT1619 can be utilized to implement trickle
current start from high voltage input sources (such as a
36V to 72V telecom bus). The trickle current start-up
circuit in Figure 11 is modified from the UVLO circuit of
Figure 10. R10 is a high value resistor that charges the
storage capacitor C2 during start-up. Before V
the upper UVLO trip point, Q2 holds the S/S pin low. The
LT1619 draws shutdown mode current ( 15 A) from V
Q2 collector can also be tied to the V
as in Figure 10. The LT1619 will then draw idle mode
quiescent current ( 140 A) from V
to charge C2 while supplying current to the UVLO circuit
and the LT1619. Maximizing R5 to R9 values reduces
power dissipation in R10.
When V
starts switching and its current consumption increases.
Before the bootstrap takes over, the LT1619 draws its
current from C2. V
threshold. Increasing the value of C2 allows more time for
the bootstrap circuit to establish itself before the converter
enters undervoltage lockout.
HV V
C2
IN
Figure 11. Trickle Current Start-Up with Bootstrapped V
R5
R6
CC
R10
crosses the upper UVLO threshold, the LT1619
R8
Q1
R7
R9
CC
Q2
ramps towards the lower UVLO
V
CC
1
2
3
4
S/S
FB
V
GND
C
LT1619
CC
SENSE
GATE
C
DRV
1619 F11
. R10 should be able
V
pin through a diode
IN
8
7
6
5
LT1619
D2
CC
BOOTSTRAP
reaches
WINDING
11
T1
CC
1619fa
CC
IN
.