LP2975IMMX-3.3 National Semiconductor, LP2975IMMX-3.3 Datasheet - Page 12

• Manufacturer Part Number: LP2975IMMX-3.3
• Description: IC DRIVER/CONTR MOSFET LDO 8MSOP
• Manufacturer: National Semiconductor
• Type: Positive Fixedr

Specifications of LP2975IMMX-3.3

• Number Of Outputs: 1
• Voltage - Output: 3.3V
• Current - Supply: 180µA
• Voltage - Input: 1.8 ~ 24 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LP2975IMMX-3.3

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Application Hints
1) The Gate pin of the LP2975 (which drives the Gate of the
FET) has a limited amount of current to source or sink. This
means faster changes in Gate voltage (which corresponds to
faster transient response) will occur with a smaller amount of
Gate capacitance.
2) The Gate capacitance forms a pole in the loop gain which
can reduce phase margin. When possible, this pole should
be kept at a higher frequency than the cross-over frequency
of the regulator loop (see later section CROSS-OVER FRE-
QUENCY AND PHASE MARGIN).
A high value of Gate capacitance may require that a feed-
forward capacitor be used to cancel some of the excess
phase shift (see later section FEED-FORWARD CAPACI-
TOR) to prevent loop instability.
POWER DISSIPATION: The maximum power dissipated in
the FET in any application can be calculated from:
Where the term I
should be noted that if the regulator is to be designed to
withstand short-circuit, a current sense resistor must be
used to limit I
CIRCUIT CURRENT LIMITING).
The power dissipated in the FET determines the best choice
for package type. A TO-220 package device is best suited for
applications where power dissipation is less than 15W.
Power levels above 15W would almost certainly require a
TO-3 type device.
In low power applications, surface-mount package devices
are size-efficient and cost-effective, but care must be taken
to not exceed their power dissipation limits.
POWER DISSIPATION AND HEATSINKING
Since the LP2975 controller is suitable for use with almost
any external P-FET, it follows that designs can be built which
have very high power dissipation in the pass FET. Since the
controller can not protect the FET from overtemperature
damage, thermal design must be carefully done to assure a
reliable design.
THERMAL DESIGN METHOD: The temperature of the FET
and the power dissipated is defined by the equation:
Where:
T
T
P
θ
To ensure a reliable design, the following guidelines are
recommended:
1) Design for a maximum (worst-case) FET junction tem-
perature which does not exceed 150˚C.
2) Heatsinking should be designed for worst-case (maxi-
mum) values of T
3) In designs which must survive a short circuit on the output,
the maximum power dissipation must be calculated assum-
ing that the output is shorted to ground:
Where I
4) If the design is not intended to be short-circuit proof, the
maximum power dissipation for intended operation will be:
J-A
J
A
D
is the junction temperature of the FET.
is the ambient temperature.
is the power dissipated by the FET.
is the junction-to-ambient thermal resistance.
SC
is the short-circuit output current.
MAX
P
D
P
(MAX) = (V
MAX
A
to a safe value (refer to section SHORT-
MAX
T
P
and P
J
D
= (V
(MAX) = V
= (θ
is the maximum output current. It
D
IN
J-A
.
IN
− V
x P
− V
(Continued)
OUT
IN
D
) + T
OUT
x I
) x I
SC
) x I
A
MAX
MAX
12
Where I
LOW POWER (
some type of small surface-mount device will be used for the
FET in low power designs. Because of the increased cell
density (and tiny packages) used by modern FET’s, the
current carrying capability may easily exceed the power
dissipation limits of the package. It is possible to parallel two
or more FET’s, which divides the power dissipation among
all of the packages.
It should be noted that the “heatsink” for a surface mount
package is the copper of the PC board and the package itself
(direct radiation).
Surface-mount devices have the value of θ
typical PC board mounting on their data sheet. In most cases
it is best to start with the known data for the application (P
T
value will define the type of FET and, possibly, the heatsink
required for cooling.
DESIGN EXAMPLE: A design is to be done with V
and V
Based on these conditions, power dissipation in the FET
during normal operation would be:
Solving, we find that P
mum allowable value of T
70˚C, the value of θ
However, if this design must survive a continuous short on
the output, the power dissipated in the FET is higher:
(This assumes the current sense resistor is selected for an
I
The value of θ
is calculated to be 49˚C/W.
Having solved for the value(s) of θ
lected. It should be noted that a FET must be used with a
θ
HIGH POWER (≥2W) APPLICATIONS: As power dissipa-
tion increases above 2W, a FET in a larger package must be
used to obtain lower values of θ
derived in the previous section are used to calculate P
θ
Having found θ
value of θ
that a heatsink can be selected:
Where:
θ
rameter is the measure of thermal resistance between the
semiconductor die inside the FET and the surface of the
case of the FET where it mounts to the heatsink (the value of
θ
FET in a TO-220 package will have a θ
mately 2–4˚C/W, while a device in a TO-3 package will be
about 0.5–2˚C/W.
θ
measures how much thermal resistance exists between the
surface of the FET and the heatsink. θ
the package type and mounting method. A TO-220 package
with mica insulator and thermal grease secured to a heatsink
will have a θ
package mounted in the same manner will have a θ
SC
J-A
J-A
J-C
J-C
C-S
A
, T
value that is 10% higher than the required 0.3A).
.
value less than or equal to the calculated value.
can be found on the data sheet for the FET). A typical
is the junction-to-case thermal resistance. This pa-
J
is the case-to-heatsink thermal resistance, which
) and calculate the required value of θ
OUT
MAX
S-A
P
= 3.3V with a maximum load current of 300 mA.
D
is the maximum output current.
(SC) = V
(the heatsink-to-ambient thermal resistance) so
C-S
J-A
J-A
P
θ
θ
value in the range of 1–1.5˚C/W. A TO-3
<
required to survive continuous short circuit
S-A
D
J-A
, it becomes necessary to calculate the
2W) APPLICATIONS: In most cases,
= (V
J-A
= (T
= θ
IN
D
is found to be 157˚C/W.
x I
IN
J-A
= 0.51W. Assuming that the maxi-
J
J
SC
− V
is 150˚C and the maximum T
− T
− (θ
= 5 x 0.33 = 1.65W
OUT
A
)/P
J-C
) x I
D
J-A
+ θ
(MAX)
J-A
. The same formulae
LOAD
C-S
, a FET can be se-
J-C
C-S
)
J-A
value of approxi-
is dependent on
J-A
specified for a
needed. This
C-S
IN
D
value
= 5V
and
A
D
is
,