AD652JP-REEL7 Analog Devices Inc, AD652JP-REEL7 Datasheet - Page 7
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AD652JP-REEL7
Manufacturer Part Number
AD652JP-REEL7
Description
IC V-F CONV SYNCH MONO 5V 20PLCC
Manufacturer
Analog Devices Inc
Type
Voltage to Frequencyr
Datasheet
1.AD652JPZ.pdf
(28 pages)
Specifications of AD652JP-REEL7
Rohs Status
RoHS non-compliant
Frequency - Max
2MHz
Full Scale
±25ppm/°C
Linearity
±0.005%
Mounting Type
Surface Mount
Package / Case
20-LCC (J-Lead)
Converter Function
VFC
Full Scale Frequency
2000
Power Supply Requirement
Single/Dual
Single Supply Voltage (max)
36V
Single Supply Voltage (min)
12V
Dual Supply Voltage (typ)
±15V
Dual Supply Voltage (min)
±6V
Dual Supply Voltage (max)
±18V
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD652JP-REEL7
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Figure 4 shows that the period between output pulses is
constrained to be an exact multiple of the clock period.
Consider an input current of exactly one quarter the value of
the reference current. In order to achieve a charge balance, the
output frequency equals the clock frequency divided by four:
one clock period for reset and three clock periods of integrate.
This is shown in Figure 5. If the input current is increased by a
very small amount, the output frequency should also increase
by a very small amount. Initially, however, no output change is
observed for a very small increase in the input current. The
output frequency continues to run at one quarter of the clock,
delivering an average of 250 µA to the summing junction. Since
the input current is slightly larger than this, charge accumulates
in the integrator and the sawtooth signal starts to drift down-
ward. As the integrator sawtooth drifts down, the comparator
threshold is crossed earlier and earlier in each successive cycle,
until finally, a whole cycle is lost. When the cycle is lost, the
integrate phase lasts for two periods of the clock instead of the
usual three periods. Thus, among a long string of divide-by-
fours, an occasional divide-by-three occurs; the average of the
output frequency is very close to one quarter of the clock, but
the instantaneous frequency can be very different.
V
IN
R
IN
COMPARATOR
INTEGRATOR
1mA
INTEGRATOR
OUTPUT
D FLOP
CLOCK
H
LATCH
–V
FREQ
AND
OUT
OUT
OUT
OUT
OUT
Figure 4. Block Diagram and System Waveforms
S
L
C
INT
COMPARATOR
5V
Rev. C | Page 7 of 28
t
OS
THRESHOLD
AND
D FLOP
INTEGRATOR
Because of this, it is very difficult to observe the waveform on
an oscilloscope. During all of this time, the signal at the output
of the integrator is a sawtooth wave with an envelope that is also
a sawtooth. See Figure 6.
D
CLOCK IN
CK
CLOCK
Q
OUT
Figure 6. Integrator Output for I
D
G Q
LATCH
Q
t
Figure 5. Integrator Output for I
OS
THRESHOLD
SHOT
ONE
C
OS
IN
Slightly Greater than 250 µs
IN
= 250 µA
200µs/BOX
100µs/BOX
FREQ OUT
10µs/BOX
CLOCK IN
10µs/BOX
AD652
C
INT