ADT7460ARQZ ON Semiconductor, ADT7460ARQZ Datasheet - Page 44
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ADT7460ARQZ
Manufacturer Part Number
ADT7460ARQZ
Description
IC REMOTE THRML/FAN CTRLR 16QSOP
Manufacturer
ON Semiconductor
Series
dBCool®r
Specifications of ADT7460ARQZ
Function
Fan Control, Temp Monitor
Topology
ADC, Comparator, Multiplexer, Register Bank
Sensor Type
External & Internal
Sensing Temperature
-40°C ~ 120°C, External Sensor
Output Type
SMBus™
Output Alarm
No
Output Fan
Yes
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 120°C
Mounting Type
Surface Mount
Package / Case
16-QSOP
Full Temp Accuracy
+/- 3 C
Digital Output - Bus Interface
Serial (3-Wire)
Maximum Operating Temperature
+ 120 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADT7460ARQZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
ADT7460ARQZ-REEL
Manufacturer:
ST
Quantity:
16
ADT7460
Table 60. Register 0x63—
Bit
<2:0>
<3>
<6:4>
<7>
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no
effect.
Table 61. PWM Min Duty Cycle Registers
Register Address
0x64
0x65
0x66
These registers become read-only when the ADT7460 is in automatic fan control mode.
Table 62. PWM Min Duty Cycle Register Bits
Bit
<7:0>
Name
ACOU3
EN3
ACOU2
EN2
Name
PWM Duty Cy
R/W
Read/Write
Read/Write
Read/Write
Read/Write
cle
Enhance Acoustics Register 2 (Power-On Default = 0x00)
R/W
Read/Write
Read/Write
Read/Write
Read/Wr
Read
Description
Th
its
en
Time Slot Increase
000
001
010
011
100
101
110
111
When this bit is 1, acoustic
T
it
e
Time Slot Increase
000
001
010
011
100
101
110
111
When this bit is 1, acoustic enhancement is enabled on PWM2 output.
hese bits sele
nhances the
s newly calcula
ese bits sele
hances the a
/Wri
newly calcu
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
ite
te
1
2
3
5
8
12
24
48
1
2
3
5
8
12
24
48
Description
PWM1 Min Duty Cycle
PWM2 Min Duty Cycle
PWM3 Min Duty Cycle
Descript
These bits define th
0x00
0x40
0x80
0x
acoustics of
ct the ramp r
lated speed,
ct the ramp
coustics of t
FF
ted speed
=
=
=
=
ion
0% Duty
25
50% Duty Cycle
1
, PWM2 ramps grace
the fans being driven by
rate applied to the PWM
00% Duty C
enhancement
he fan being driven by the
PWM3 ramps gracefully at
ate applied to the PWM3 out
Rev. C | Page 44 of 52
% Duty Cy
e PWM
Time for 33% to 100%
35 s
17.6 s
11.8 s
7 s
4.4 s
3 s
1.6 s
0.8 s
Time for 33% to 100%
35 s
17.6 s
11.8 s
7 s
4.4 s
3 s
1.6 s
0.8 s
Cyc
le (Fan Off)
cle
ycle (Fan Full Speed)
MIN
is enabled on PWM3 outpu
Power-On Default
0x80 (50% duty cycle)
0x80 (50% duty cycle)
0x80 (50% duty cycle)
duty cycle for PWMx.
fully at the rate determ
2 output. Instead
the PWM2 outpu
the rate determin
PWM3 output.
put. Instead of
t.
t.
of PWM2 jump
ined by these
PWM3 jumpin
ed by these b
ing instantaneously to
bits. This effect
its. This effect
g instantaneously to