ADT7461AR-REEL7 ON Semiconductor, ADT7461AR-REEL7 Datasheet - Page 15

• Manufacturer Part Number: ADT7461AR-REEL7
• Description: IC SENSOR TEMP 2-CH 8SOIC
• Manufacturer: ON Semiconductor

Specifications of ADT7461AR-REEL7

• Rohs Status: RoHS non-compliant
• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: 0°C ~ 127°C, External Sensor
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 120°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)

SERIAL BUS INTERFACE
Control of the ADT7461 is carried out via the serial bus. The
ADT7461 is connected to this bus as a slave device, under the
control of a master device.
After a conversion sequence completes, there should be no
SMBus transactions to the ADT7461 for at least one conversion
time, to allow the next conversion to complete. The conversion
time depends on the value programmed in the conversion rate
register.
The ADT7461 has an SMBus timeout feature. When this is
enabled, the SMBus times out typically after 25 ms of inactivity.
However, this feature is not enabled by default. Bit 7 of the
consecutive alert register (Address = 0x22) should be set to
enable it.
Consult the SMBus 1.1 specification for more information
(www.smbus.org).
ADDRESSING THE DEVICE
In general, every SMBus device has a 7-bit device address,
except for some devices that have extended 10-bit addresses.
When the master device sends a device address over the bus,
the slave device with that address responds. The ADT7461 is
available with one device address, 0x4C (1001 100b). The
ADT7461-2 is also available with one device address, 0x4D
(1001 101b)
The serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDATA, while the serial clock line SCLK remains
high. This indicates that an address/data stream will follow.
All slave peripherals connected to the serial bus respond to
the start condition and shift in the next eight bits, consist-
ing of a 7-bit address (MSB first) plus an R/W bit, which
determines the direction of the data transfer, that is,
whether data will be written to or read from the slave
device. The peripheral whose address corresponds to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the acknowledge bit. All other devices on the bus now
remain idle while the selected device waits for data to be
read from or written to it. If the R/W bit is a 0, the master
writes to the slave device. If the R/W bit is a 1, the master
reads from the slave device.
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2.
3.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation. With the ADT7461, write operations
contain either one or two bytes, while read operations contain
one byte.
To write data to one of the device data registers or to read data
from it, the address pointer register must be set so that the
correct data register is addressed. The first byte of a write
operation always contains a valid address that is stored in the
address pointer register. If data is to be written to the device, the
write operation contains a second data byte that is written to the
register selected by the address pointer register.
This is illustrated in Figure 17. The device address is sent over
the bus followed by R/W set to 0. This is followed by two data
bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the address pointer
register. The second data byte is the data to be written to the
internal data register. The examples shown in Figure 17 to
Figure 19 use the ADT7461 SMBus Address 0x4C.
Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, since a low-to-high transition
when the clock is high may be interpreted as a stop signal.
The number of data bytes that can be transmitted over the
serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
When all data bytes have been read or written, stop condi-
tions are established. In write mode, the master pulls the
data line high during the tenth clock pulse to assert a stop
condition. In read mode, the master device overrides the
acknowledge bit by pulling the data line high during the
low period before the ninth clock pulse. This is known as
a no acknowledge. The master then takes the data line low
during the low period before the tenth clock pulse, then
high during the tenth clock pulse to assert a stop condition.
ADT7461