ADT7316ARQ-REEL7 Analog Devices Inc, ADT7316ARQ-REEL7 Datasheet - Page 40

• Manufacturer Part Number: ADT7316ARQ-REEL7
• Description: IC SENSOR TEMP 12BIT DAC 16QSOP
• Manufacturer: Analog Devices Inc

Specifications of ADT7316ARQ-REEL7

• Rohs Status: RoHS non-compliant
• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 120°C, External Sensor
• Output Type: I²C™, MICROWIRE™, QSPI™, SMBus™, SPI™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 120°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• For Use With: EVAL-ADT7316EBZ - BOARD EVAL FOR ADT7316
• Lead Free Status / RoHS Status: Not Compliant

ADT7316/ADT7317/ADT7318
SMBUS/SPI INT/ INT
The ADT7316/ADT7317/ADT7318 INT/ INT output is an
interrupt line that signals an over-limit/under-limit event on
any of the measurement channels if the interrupt on that event
has not been disabled. The ADT7316/ADT7317/ADT7318 are
slave-only devices and use the SMBus/SPI INT/ INT as their
only means to signal other devices that an event has occurred.
The INT/ INT pin has an open-drain configuration that allows
the outputs of several devices to be wire-AND’ e d together when
the INT/ INT pin is active low. Use C6 of the Control Configu-
ration 1 register (Address 0x18) to set the active polarity of the
INT/ INT output. The power-up default is active low. The INT/
INT output can be disabled or enabled by setting C5 of the
Control Configuration 1 register (Address 0x18) to 1 or 0,
respectively.
The INT/ INT output becomes active when either the internal
temperature value, the external temperature value, or the V
value exceeds the values in their corresponding T
T
when a conversion result indicates that all measurement channels
are within their trip limits, and when the status register associ-
ated with the out-of-limit event is read. The two interrupt status
registers show which event caused the INT/ INT pin to go active.
The INT/ INT output requires an external pull-up resistor. This
can be connected to a voltage different from V
the maximum voltage rating of the INT/ INT output pin is not
exceeded. The value of the pull-up resistor depends on the
application but should be large enough to avoid excessive sink
currents at the INT/ INT output, which can heat the chip and
affect the temperature reading.
SMBUS Alert Response
The INT/ INT pin behaves the same way as a SMBus alert pin
when the SMBus/I
output and requires a pull-up to V
can be wire-AND’ e d together so that the common line goes low
if one or more of the INT/ INT outputs goes low. The polarity
of the INT/ INT pin must be set for active low for a number of
outputs to be wire-AND’ e d together. The INT/ INT output can
operate as a SMBALERT function. Slave devices on the SMBus
typically cannot signal to the master that they want to talk, but
the SMBALERT function allows them to do so. SMBALERT is
used in conjunction with the SMBus general call address.
LOW
/V
LOW
registers. The INT/ INT output goes inactive again
2
C interface is selected. It is an open-drain
DD
. Several INT/ INT outputs
DD
provided that
HIGH
/V
HIGH
DD
or
Rev. B | Page 40 of 44
One or more INT/ INT outputs can be connected to a common
SMBALERT line connected to the master. When a SMBALERT
line is pulled low by one of the devices, the following procedure
occurs (see Figure 59).
1. SMBALERT is pulled low.
2. The master initiates a read operation and sends the alert
3. The devices whose INT/ INT output is low respond to the
4. If more than one devices INT/ INT output is low, the one
5. Once the ADT7316/ADT7317/ADT7318 has responded
START
MASTER
RECEIVES
SMBALERT
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
alert response address and the master reads its device
address. Because the device address is 7 bits long, an LSB
of 1 is added. The address of the device is now known and
it can be interrogated in the usual way.
with the lowest device address has priority, in accordance
with typical SMBus specifications.
to the alert response address, it resets its INT/ INT output,
provided that the condition that caused the out-of-limit
event no longer exists and the status register associated with
the out-of-limit event is read. If the SMBALERT line remains
low, the master sends the ARA again. It continues to do this
until all devices whose SMBALERT outputs were low have
responded.
START
MASTER
RECEIVES
SMBALERT
ALERT RESPONSE
ALERT RESPONSE
MASTER SENDS
Figure 60. INT/ INT Responds to SMBALERT ARA with
ARA AND READ
ADDRESS
MASTER SENDS
ARA AND READ
Figure 59. INT/ INT Responds to SMBALERT ARA
COMMAND
ADDRESS
COMMAND
Packet Error Checking (PEC)
RD ACK
DEVICE ACK
RD ACK DEVICE ADDRESS
DEVICE SENDS
ITS ADDRESS
ADDRESS
DEVICE
DEVICE SENDS
ITS ADDRESS
MASTER
ACK
ACK
DEVICE SENDS
ITS PEC DATA
PEC
ACK
MASTER
NO
NACK
ACK
NO
STOP
STOP