ADT7462ACPZ-REEL ON Semiconductor, ADT7462ACPZ-REEL Datasheet - Page 51

• Manufacturer Part Number: ADT7462ACPZ-REEL
• Description: IC TEMP/VOLT MONITOR 32-LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADT7462ACPZ-REEL

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Number Of Voltages Monitored: 1
• Monitored Voltage: 0.9 V to 12 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (typ): 4000 uA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

corresponding bit in the GPIO status register becomes
read/write. Setting this bit then asserts the GPIO output.
(Again, “asserted” can be high or low, depending on the
setting of the polarity bit.) The effect of a GPIO status
register bit on the ALERT output can be masked by setting
the corresponding bit in one of the GPIO mask registers.
corresponding status bit is automatically masked to prevent
the data written to the status bit from causing an interrupt.
When configured as inputs, the GPIO pins can be connected
to external interrupt sources such as temperature sensors
with digital output.
EDO Circuitry
assertion of one of the four GPIOs (GPIO1 to GPIO4) can
be used to latch one of the two EDOs high or low. The
ADT7462 has two EDO event mask registers (0x37 and
0x38): one mask for each EDO. See Table 29 for an
explanation of event mask register functionality.
can be used to set or reset either one of the two EDO outputs.
ADT7462 drive LEDs or signals based on rules. For
example, if a GPIO1 (power fail), a GPIO2 (overcurrent), or
an overtemperature condition occurs, EDO1 (power supply
fault LED) can be latched. This does not require software
handling and makes the part more autonomous.
Other Digital Inputs
can be found on PC motherboards. These inputs can be
Table 29. EDO Control (Mask) Register 0x37 and Register 0x38
0 = Drive Output X
1 = Ignore Event
When a GPIO pin is configured as an output, the
When the pin is configured as an output, the
The ADT7462 has the added functionality that the
Table 29 shows that any of the four designated GPIO pins
Using this functionality, it is possible to have the
The ADT7462 contains other specific digital inputs that
Undervoltage
Overvoltage/
Bit 7:
0 = Drive Output X
1 = Ignore Event
Bit 6: THERM
0 = Drive Output X
1 = Ignore Event
Bit 5: Fan Fail
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51
Bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
registers (0x09 and 0x0A).
registers makes the corresponding GPIO pin active high.
allow the EDO output to be driven high or low (depending
on the polarity bit of the configuration register) and latched
(depending on the EDO latch bit of the configuration
register), if the ADT7462 detects an overtemperature, an
over/undervoltage, or a fan failure condition.
monitored and configured for actions to occur on their
assertion.
VR_HOT Inputs
These are specific digital signals from the CPU voltage
regulator that indicate an overtemperature. On assertion of
these inputs, the relevant status bits are set in Thermal Status
Register 2 (Host Register 0xB9 or BMC Register 0xC1).
Assertion of these inputs can also be used to boost the fans
to full speed, thus providing emergency cooling in the event
of VR overtemperature. This is set using Bit 3 (VRD1) and
The polarity of the EDOs is set in the GPIO configuration
Setting a polarity bit to 1 in one of the GPIO configuration
Clearing the polarity bit to 0 makes it active low.
Bits [7:5] of each event mask register (0x37 and 0x38)
Pin 25 and Pin 26 can be configured as VR_HOT inputs.
Bit 2
GPIO1
GPIO2
GPIO3
GPIO4
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Figure 84. EDO Circuit
Bit 0
LATCH
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G4 or G3 or G2 or G1
G4 or G3 or G2
G4 or G3 or G1
G4 or G3
G4 or G2 or G1
G4 or G2
G4 or G1
G4
G3 or G2 or G1
G3 or G2
G3 or G1
G3
G2 or G1
G2
G1
GPIO events ignored by Output X
Latches Output X (G = GPIO)
Behavior: What Drives and
EVENT
MASK
EDO (GPIO5)
EDO (GPIO6)