ADT7473ARQZ-RL7 ON Semiconductor, ADT7473ARQZ-RL7 Datasheet - Page 30

• Manufacturer Part Number: ADT7473ARQZ-RL7
• Description: IC REMOTE THERMAL CTLR 16QSOP
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of ADT7473ARQZ-RL7

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Full Temp Accuracy: +/- 0.5 C
• Digital Output - Bus Interface: Serial (3-Wire, 4-Wire)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Sleep States
designed to operate from a 3.3 V STBY supply. In computers
that support S3 and S5 states, the core voltage of the
processor is lowered in these states. If using the dynamic
T
changes the CPU temperature and the dynamics of the
system under dynamic T
monitoring THERM, the THERM timer should be disabled
during these states.
Dynamic T
VCCPLO = 1
the following occurs:
limit, everything is re−enabled, and the system resumes
normal operation.
XNOR Tree Test Mode
mode. This mode is useful for in−circuit test equipment at
board−level testing. By applying stimulus to the pins
included in the XNOR tree, it is possible to detect opens or
shorts on the system board.
XNOR tree test mode. The XNOR tree test is invoked by
setting Bit 0 (XEN) of the XNOR tree test enable register
(0x6F).
Power−On Default
input. By default, the ADT7473−1 powers up with fans
running, eliminating the need for polling of V
is not powered up), the ADT7473 assumes the functionality
MIN
The ADT7473/ADT7473−1 has been specifically
When the V
Once the core voltage, V
The ADT7473/ADT7473−1 includes an XNOR tree test
Figure 45 shows the signals that are exercised in the
When the ADT7473 is powered up, it polls the V
If V
1. Status Bit 1 (V
2. SMBALERT is generated, if enabled.
3. THERM monitoring is disabled. The THERM
4. Dynamic T
5. The ADT7473/ADT7473−1 is prevented from
CCP
mode, lowering the core voltage of the processor
timer should hold its value prior to the S3 or S5
state.
T
entering the shutdown state.
MIN
stays below 0.75 V (the system CPU power rail
MIN
from being adjusted due to an S3 or S5 state.
CCP
Figure 45. XNOR Tree Test
Control Register 1 (0X36) Bit [1]
TACH1
TACH2
TACH3
TACH4
PWM2
PWM3
voltage drops below the V
MIN
CCP
control is disabled. This prevents
) in Status Register 1 is set.
MIN
CCP
, goes above the V
PWM1/XTO
control. Likewise, when
CCP
CCP
low limit,
.
CCP
http://onsemi.com
low
CCP
30
of the default registers after the ADT74731 is addressed via
any valid SMBus transaction.
powered up), a fail−safe timer begins to count down. If the
ADT7473 is not addressed by any valid SMBus transactions
before the fail−safe timeout (4.6 seconds) lapses, the
ADT7473 drives the fans to full speed. If the ADT7473 is
addressed by a valid SMBus transaction after this point, the
fans stop, and the ADT7473 assumes its default settings and
begins normal operation.
powered up), then a fail−safe timer begins to count down. If
the ADT7473 is addressed by a valid SMBus transaction
before the fail−safe timeout (4.6 seconds) lapses, then the
ADT7473 operates normally, assuming the functionality of
all the default registers. See the flow chart in Figure 46.
Programming the Automatic Fan Speed Control Loop
strongly recommended to use the ADT7473/ADT7473−1
evaluation board and software while reading this section.
understanding of the automatic fan control loop, and
provides step−by−step guidance on effectively evaluating
and selecting critical system parameters. To optimize the
system characteristics, the designer needs to consider the
system configuration, including the number of fans, where
they are located, and what temperatures are measured in the
particular system.
Y
Y
If V
If V
To understand the automatic fan speed control loop, it is
This section provides the system designer with an
ADT7473/ADT7473−1 IS POWERED UP
AFTER THE FAIL−SAFE TIMEOUT
ADT7473/ADT7473−1 NORMALLY
HAS THE ADT7473/ADT7473−1
BEEN ACCESSED BY A VALID
HAS THE ADT7473/ADT7473−1
BEEN ACCESSED BY A VALID
HAS THE ADT7473/ADT7473−1
BEEN ACCESSED BY A VALID
FAIL−SAFE TIMER ELAPSES
CCP
CC
START FAIL−SAFE TIMER
SMBus TRANSACTION?
SMBus TRANSACTION?
SMBus TRANSACTION?
IS V
goes high (the system processor power rail is
CCP
START UP THE
goes high (the system processor power rail is
Figure 46. Power−On Flow Chart
ABOVE 0.75V?
N
Y
N
Y
N
N
HAS THE ADT7473/ADT7473−1
BEEN ACCESSED BY A VALID
SMBus TRANSACTION?
SWITCH OFF FANS
RUNS THE FANS
TO FULL SPEED
CHECK V
Y
CCP
N