ADT75ARMZ Analog Devices Inc, ADT75ARMZ Datasheet - Page 16

• Manufacturer Part Number: ADT75ARMZ
• Description: IC TEMP SENSOR DGTL 12BIT 8-MSOP
• Manufacturer: Analog Devices Inc
• Type: HW Monitorsr

Specifications of ADT75ARMZ

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Comparator, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -55°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Ic Output Type: Digital
• Sensing Accuracy Range: ± 2°C
• Supply Current: 380µA
• Supply Voltage Range: 3V To 5.5V
• Resolution (bits): 12bit
• Sensor Case Style: MSOP
• No. Of Pins: 8
• Msl: MSL 3 - 168 Hours
• Temperature Sensor Function: Temp Sensor
• Resolution: 12b
• Package Type: MSOP
• Operating Temperature (min): -55
• Operating Temperature (max): 125C
• Operating Temperature Classification: Military
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADT75
SERIAL INTERFACE
Control of the ADT75 is carried out via the SMBus/I
compatible serial interface. The ADT75 is connected to this bus
as a slave and is under the control of a master device.
Figure 13 shows a typical SMBus/I
Serial Bus Address
Like all SMBus/I
serial address. The four MSBs of this address for the ADT75 are
set to 1001. Pin A2, Pin A1, and Pin A0 set the three LSBs.
These pins can be configured two ways, low and high, to give
eight different address options. Table 12 shows the different bus
address options available. Recommended pull-up resistor value
on the SDA and SCL lines is 10 kΩ .
Table 12. SMBus/I
Binary
A6
1
1
1
1
1
1
1
1
The ADT75 is designed with a SMBus/I
SMBus/I
activity on the SDA line. After this timeout, the ADT75 resets
the SDA line back to its idle state (SDA set to high impedance)
and wait for the next start condition.
A5
0
0
0
0
0
0
0
0
10kΩ
PULL-UP
2
C interface times out after 75 ms to 325 ms of no
V
DD
Figure 13. Typical SMBus/I
A4
0
0
0
0
0
0
0
0
OS/ALERT
A0
A1
A2
2
C-compatible devices, the ADT75 has a 7-bit
ADT75
2
A3
1
1
1
1
1
1
1
1
C Bus Address Options
GND
SDA
SCL
A2
0
0
0
0
1
1
1
1
V
SMBus/I
DD
2
A1
0
0
1
1
0
0
1
1
C Interface Connection
0.1μF
2
C interface connection.
10kΩ
2
PULL-UP
C ADDRESS = 1001 000
2
A0
0
1
0
1
0
1
0
1
V
C timeout. The
DD
10kΩ
Hex
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
2
C-
Rev. A | Page 16 of 24
The serial bus protocol operates as follows:
1.
2.
3.
4.
Any number of bytes of data can be transferred over the serial
bus in one operation. However, it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
The I
the device until after this address has been sent twice. On the eighth
SCL cycle of the second valid communication, the serial
bus address is latched in. This is the SCL cycle directly after
the device has seen its own I
changes on this pin has no effect on the I
The master initiates data transfer by establishing a start
condition, defined as a high to low transition on the serial
data line SDA, while the serial clock line SCL remains high.
This indicates that an address/data stream is going to
follow. All slave peripherals connected to the serial bus
respond to the start condition and shift in the next eight
bits, consisting of a 7-bit address (MSB first) plus a
read/write (R/W) bit. The R/W bit determines whether
data is written to, or read from, the slave device.
The peripheral with the address corresponding to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the acknowledge bit. All other devices on the bus now
remain idle while the selected device waits for data to be
read from or written to it. If the R/W bit is a zero then the
master writes to the slave device. If the R/W bit is a one
then the master reads from the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the receiver of data. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low to high transition
when the clock is high can be interpreted as a stop signal.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10
stop condition. In read mode, the master device pulls the
data line high during the low period before the ninth clock
pulse. This is known as no acknowledge. The master takes
the data line low during the low period before the 10
clock pulse, then high during the 10
a stop condition.
2
C address set up by the three address pins is not latched by
2
C serial bus address. Any subsequent
th
clock pulse to assert a
2
C serial bus address.
th
clock pulse to assert
th