ADT7475ARQZ ON Semiconductor, ADT7475ARQZ Datasheet
ADT7475ARQZ
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ADT7475ARQZ Summary of contents
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ADT7475 R dBCOOL Remote Thermal Monitor and Fan Controller The ADT7475 dBCOOL controller is a thermal monitor and multiple PWM fan controller for noise−sensitive or power−sensitive applications requiring active system cooling. The ADT7475 can drive a fan using either a ...
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PWM PWM1 REGISTERS PWM2 CONTROLLERS PWM3 (HF AND LF) TACH1 TACH2 TACH3 TACH4 THERM V TO ADT7475 D1+ D1– D2+ D2– V CCP BAND GAP TEMPERATURE SENSOR ABSOLUTE MAXIMUM RATINGS Parameter Positive Supply Voltage ( ...
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PIN ASSIGNMENT Pin No. Mnemonic 1 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pullup. 2 GND Ground Pin. 3 VCC Power Supply. VCC is also monitored through this pin TACH3 Digital Input (Open Drain). ...
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ELECTRICAL CHARACTERISTICS Parameter Power Supply Supply Voltage Supply Current Temperature−to−Digital Converter Local Sensor Accuracy Resolution Remote Diode Sensor Accuracy Resolution Remote Sensor Source Current ANALOG−TO−DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) Total Unadjusted Error (TUE) Differential Non−linearity (DNL) Power ...
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ELECTRICAL CHARACTERISTICS Parameter DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+ Input High Voltage Input Low Voltage DIGITAL INPUT CURRENT Input High Current Input Low Current Input Capacitance SERIAL BUS TIMING Clock ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 – CAPACITANCE (nF) Figure 3. Temperature Error vs. Capacitance Between D+ and D− Figure 5. Remote Temperature Error vs. Common−Mode Noise Frequency ...
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TYPICAL PERFORMANCE CHARACTERISTICS Figure 9. Remote Temperature Error vs. Power Supply Noise Frequency 3.0 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 Figure 11. Remote Temperature Error vs. ADT7475 Temperature 3.0 2.5 2.0 1.5 1.0 0.5 0 −0.5 ...
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Product Description The ADT7475 is a complete thermal monitor and multiple fan controller for any system requiring thermal monitoring and cooling. The device communicates with the system via a serial system management bus. The serial bus controller has a serial ...
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Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix ...
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It is possible to read a data byte from a data register without first writing to the address pointer register if the address pointer register is already at the correct value. However not possible to write data to ...
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SMBALERT line connected to the master device’s SMBALERT line goes low, the following events occur: 1. SMBALERT is pulled low. 2. The master initiates a read operation and sends the alert response address (ARA ...
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This effectively gives a reading 16 times faster (711 ms), but the reading may be noisier. Bypass Voltage Input Attenuator Setting Bit 5 of Configuration Register 2 (0x73) removes the attenuation circuitry from the V CCP the user to directly ...
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Temperature Measurement Method Local Temperature Measurement The ADT7475 contains an on−chip band gap temperature sensor whose output is digitized by the on−chip, 10−bit ADC. The 8−bit MSB temperature data is stored in the temperature registers (0x25, 0x26, and 0x27). Because ...
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ADT7475 2N3904 D+ NPN D– Figure 21. Measuring Temperature Using an NPN Transistor ADT7475 D+ 2N3906 D– PNP Figure 22. Measuring Temperature Using a PNP Transistor Factors ...
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Nulling Out Temperature Errors As CPUs run faster more difficult to avoid high frequency clocks when routing the D+/D– traces around a system board. Even when recommended layout guidelines are followed, some temperature errors can still be attributable ...
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Table 6. Conversion Time with Averaging Enabled Channel Measurement Time (ms) Voltage Channels Remote Temperature 1 Remote Temperature 2 Local Temperature Single−Channel ADC Conversions Setting Bit 6 of Configuration Register 2 (0x73) places the ADT7475 into single−channel ADC conversion mode. ...
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Fan Limit Registers Register 0x54, TACH1 Minimum Low Byte = 0xFF default Register 0x55, TACH1 Minimum High Byte = 0xFF default Register 0x56, TACH2 Minimum Low Byte = ...
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Bit 3 (FAN2 indicates that Fan 2 has dropped below minimum speed. Bit 2 (FAN1 indicates that Fan 1 has dropped below minimum speed. Bit 1 (OVT indicates that a THERM overtemperature limit has ...
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Table 8. Configuring Pin 5 as SMBALERT Output Register Configuration Register 3 (0x78) [0] ALERT Enable = 1 Assigning THERM Functionality to a Pin Pin 9 on the ADT7475 has four possible functions: SMBALERT, THERM, GPIO, and TACH4. The user ...
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Generating SMBALERT Interrupts from A THERM Timer Events The ADT7475 can generate SMBALERTs when a programmable THERM timer limit has been exceeded. This allows the system designer to ignore brief, infrequent THERM assertions, while capturing longer THERM timer events. Register ...
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THERM is asserting more frequently on an hourly basis. Alternatively, OS− or BIOS−level software can time−stamp when the system is powered on SMBALERT is generated due to the THERM timer limit being exceeded, ...
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Figure 30 shows how to drive a 3−wire fan using PWM control. 12V 12V 10kΩ 10kΩ TACH 4.7kΩ ADT7475 3.3V 10kΩ PWM Figure 30. Driving a ...
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Driving up to Three Fans from PWM3 TACH measurements for fans are synchronized to particular PWM channels; for example, TACH1 is synchronized to PWM1. TACH3 and TACH4 are both synchronized to PWM3, so PWM3 can drive two fans. Alternatively, PWM3 ...
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TACH input. The net result of this is that all TACH readings are locked until the high byte is read from the corresponding TACH registers. All TACH related interrupts are also ignored until the appropriate high byte ...
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TACH Pulses per Revolution Register Bits [1:0] Fan 1 default = 2 pulses per revolution. Bits [3:2] Fan 2 default = 2 pulses per revolution. Bits [5:4] Fan 3 default = 2 pulses per revolution. Bits [7:6] Fan 4 default ...
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PWM Configuration Registers (0x5C to 0x5E) Bits [7:5] BHVR 111 = manual mode. Once under manual control, each PWM output can be manually updated by writing to Register 0x30 to Register 0x32 (PWMx current duty cycle registers). Programming the PWM ...
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If V goes high (the system processor power rail is CC powered up), a fail−safe timer begins to count down. If the ADT7475 is not addressed by any valid SMBus transactions before the fail−safe timeout (4.6 seconds) lapses, the ADT7475 ...
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Step 1: Hardware Configuration During system design, the motherboard sensing and control capabilities should be addressed early in the design stages. Decisions about how these capabilities are used should involve the system thermal/mechanical engineer. Ask the following questions: 1. What ...
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Recommended Implementation 1 Configuring the ADT7475 as in Figure 44 provides the system designer with the following features: • Two PWM outputs for fan control three fans. (The front and rear chassis fans are connected in parallel.) ...
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Recommended Implementation 2 Configuring the ADT7475 as in Figure 45 provides the system designer with the following features: • Three PWM outputs for fan control three fans. (All three fans can be individually controlled.) • Three TACH ...
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Step 2: Configuring the Mux After the system hardware configuration is determined, the fans can be assigned to particular temperature channels. Not only can fans be assigned to individual channels but the behavior of the fans is also configurable. For ...
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Mux Configuration Example This is an example of how to configure the mux in a system using the ADT7475 to control three fans. The CPU fan sink is controlled by PWM1, the front chassis fan is controlled by PWM2, and ...
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Enhanced Acoustics Register 1 (0x62) Bit 7 (MIN3 PWM3 is off (0% PWM duty cycle) when temperature is below T − MIN HYST Bit 7 (MIN3 PWM3 runs at PWM3 minimum duty cycle below ...
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More than one PWM output can be controlled from a single temperature measurement channel. For example, Remote 1 temperature can control PWM1 and PWM2 outputs. If two different fans are used on PWM1 and PWM2, the fan characteristics can be ...
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Step 6: T for Temperature Channels RANGE T is the range of temperature over which automatic RANGE fan control occurs once the programmed T has been exceeded the temperature range RANGE between PWM and 100% PWM where the ...
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Actual Changes in PWM Output (Advanced Acoustics Settings) While the automatic fan control algorithm describes the general response of the PWM output, the enhanced acoustics registers (0x62 and 0x63) can be used to set/clamp the maximum rate of change of ...
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Ambient temperature drives the front chassis fan and rear chassis fan connected to PWM2 and PWM3. The front chassis fan is configured to run at PWM chassis fan is configured to run at PWM CPU fan is configured to run ...
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T 100 MIN THERMAL CALIBRATION T MIN THERMAL CALIBRATION REMOTE 2 = CPU TEMP T MIN LOCAL = THERMAL CALIBRATION VRM TEMP T MIN REMOTE 1 = AMBIENT TEMP Figure 59. How T Step 8: T for Temperature ...
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T MIN THERMAL CALIBRATION T MIN THERMAL CALIBRATION REMOTE 2 = CPU TEMP T MIN LOCAL = THERMAL CALIBRATION VRM TEMP T MIN REMOTE 1 = AMBIENT TEMP Figure 60. The T HYST Enhanced Acoustics Register 1 (0x62) ...
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Enhanced Acoustics Register 1 (0x62) Bits [2:0] (ACOU1), select the ramp rate for PWM outputs associated with the Remote 1 temperature input. 000 = 37.5 sec 001 = 18.8 sec 010 = 12.5 sec 011 = 7.5 sec 100 = ...
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Register Tables Table 11. ADT7475 Registers Addr R/W Desc Bit 7 0x10 R/W Configuration Extra Register 6 Slow 0x11 R Configuration RES Register 7 0x21 CCP Reading 0x22 R V Reading 9 CC 0x25 R Remote 1 ...
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Table 11. ADT7475 Registers Addr R/W Desc Bit 7 0x49 R/W V High 7 CC Limit 0x4E R/W Remote 1 7 Temp Low Limit 0x4F R/W Remote 1 7 Temp High Limit 0x50 R/W Local Temp 7 Low Limit 0x51 ...
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Table 11. ADT7475 Registers Addr R/W Desc Bit 7 0x65 R/W PWM2 Min 7 Duty Cycle 0x66 R/W PWM3 Min 7 Duty Cycle 0x67 R/W Remote 1 7 Temp T MIN 0x68 R/W Local Temp 7 T MIN 0x69 R/W ...
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Table 12. Register 0x10 — Configuration Register 6 (Power−On Default = 0x00) Bit No. Mnemonic R/W [0] SLOW R/W Remote 1 [1] SLOW R/W Local [2] SLOW R/W Remote 2 [3] THERM in R/W Manual [5:4] Reserved N/A [6] V ...
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Table 16. Fan Tachometer Reading Registers (Power−On Default = 0x00) Register Address R/W 0x28 Read−only 0x29 Read−only 0x2A Read−only 0x2B Read−only 0x2C Read−only 0x2D Read−only 0x2E Read−only 0x2F Read−only 1. These registers count the number of 11.11 ms periods (based ...
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Table 19. Register 0x40 — Configuration Register 1 (Power−On Default = 0x04) Bit No. Mnemonic R/W [0] R/W STRT (Notes 1, 2) [1] LOCK Write Once [2] RDY Read−only [3] FSPD R/W [4] Vx1 R/W [5] FSPDIS R/W [6] TODIS ...
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Table 21. Register 0x42 — Interrupt Status Register 2 (Power−On Default = 0x00) Bit No. Mnemonic R/W [1] OVT Read−only [2] FAN1 Read−only [3] FAN2 Read−only [4] FAN3 Read−only [5] F4P Read−only R/W Read−only [6] D1 Read−only [7] D2 Read−only ...
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Table 24. Fan Tachometer Limit Registers Register Address R/W 0x54 R/W 0x55 R/W 0x56 R/W 0x57 R/W 0x58 R/W 0x59 R/W 0x5A R/W 0x5B R/W 1. Exceeding any of the TACH limit registers by 1 indicates that the fan is ...
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Table 28. Temp T /PWM Frequency Registers RANGE Register Address R/W 0x5F R/W 0x60 R/W 0x61 R/W 1. These registers become read−only when the Configuration Register 1 lock bit is set. Any subsequent attempts to write to these registers fail. ...
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Table 30. Register 0x62 — Enhanced Acoustics Register 1 (Power−On Default = 0x00) Bit No. Mnemonic R/W (Note 1) [2:0] ACOU1 R/W When Bit 7 of Configuration Register 6 (0x10 Time Slot Increase When Bit 7 of Configuration ...
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Table 31. Register 0x63 — Enhanced Acoustics Register 2 (Power−On Default = 0x00) Bit No. Mnemonic R/W (Note 1) [2:0] ACOU3 R/W When Bit 7 of Configuration Register 6 (0x10 Time Slot Increase When Bit 7 of Configuration ...
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Table 33. Register 0x64, Register 0x65, Register 0x66 — PWM Minimum Duty Cycle Registers (Power−On Default = 0x80; 50% Duty Cycle) Bit No. Mnemonic R/W [7:0] PWM Duty R/W Cycle Table 34. T Registers (Note 1 and 2) MIN Register ...
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Table 37. XNOR Tree Test Enable Register Register Address R/W (Note 1) 0x6F R/W 1. These registers become read−only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail. Table ...
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Table 41. Register 0x73 — Configuration Register 2 (Power−On Default = 0x00) Bit No. Mnemonic R/W (Note 1) [0:3] RES [4] AVG R/W [5] ATTN R/W [6] CONV R/W Register 0x55, Bits [7:5] [7] SHDN R/W 1. These registers become ...
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Table 45. Register 0x77 — Extended Resolution Register 2 Bit No. Mnemonic R/W [3:2] TDM1 R/W [5:4] LTMP R/W [7:6] TDM2 R this register is read, this register and the registers holding the MSB of each reading are ...
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Table 49. Register 0x7B — TACH Pulses per Revolution Register (Power−On Default = 0x55) Bit No. Mnemonic R/W [1:0] FAN1 R/W [3:2] FAN2 R/W [5:4] FAN3 R/W [7:6] FAN4 R/W Table 50. Register 0x7C — Configuration Register 5 (Power−On Default ...
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... ADT7475ARQZ −40°C to +125°C ADT7475ARQZ−REEL −40°C to +125°C ADT7475ARQZ−RL7 −40°C to +125°C †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *The “Z’’ suffix indicates Pb−Free part. ...
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