DS1722U+ Maxim Integrated Products, DS1722U+ Datasheet - Page 7

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DS1722U+

Manufacturer Part Number
DS1722U+
Description
IC THERMOMETER DIG 3-WIRE 8-USOP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS1722U+

Function
Thermometer, Thermostat
Topology
ADC, Register Bank
Sensor Type
Internal
Sensing Temperature
-55°C ~ 120°C
Output Type
SPI™
Output Alarm
No
Output Fan
No
Voltage - Supply
2.65 V ~ 5.5 V
Operating Temperature
-55°C ~ 120°C
Mounting Type
Surface Mount
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Full Temp Accuracy
+/- 2 C
Digital Output - Bus Interface
3-Wire, SPI
Digital Output - Number Of Bits
12 bit
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.65 V, 1.8 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Supply Current
0.5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
inactive clock is determined by sampling SCLK when CE becomes active. Therefore, either SCLK
polarity can be accommodated. Input data (SDI) is latched on the internal strobe edge and output data
(SDO) is shifted out on the shift edge (See Table 6 and Figure 3). There is one clock for each bit
transferred. Address and data bits are transferred in groups of eight, MSB first.
FUNCTION TABLE Table 6
*CPOL is the “Clock Polarity” bit that is set in the control register of the microcontroller.
** SDO remains at High Z until eight bits of data are ready to be shifted out during a read.
NOTE:
CPHA bit polarity must be set to “1”.
SERIAL CLOCK AS A FUNCTION OF MICROCONTROLLER CLOCK
POLARITY (CPOL) Figure 3
CPOL=1
CPOL=0
NOTE:
CPOL is a bit that is set in the microcontroller’s Control Register.
ADDRESS AND DATA BYTES
Address and data bytes are shifted MSB first into the serial data input (SDI) and out of the serial data
output (SDO). Any transfer requires the address of the byte to specify a write or a read, followed by one
or more bytes of data. Data is transferred out of the SDO for a read operation and into the SDI for a write
operation.
Disable Reset
Write
Read
MODE
SCLK
SCLK
CE
CE
CE
H
H
L
Input Disabled
CPOL=1*
CPOL=0
CPOL=1
CPOL=0
SCLK
7 of 14
SHIFT
SHIFT
Input Disabled
Data Bit Latch
X
INTERNAL
STROBE
INTERNAL
STROBE
SDI
High Z
High Z
shift**
Next data bit
SDO

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