LM87CIMT/NOPB National Semiconductor, LM87CIMT/NOPB Datasheet - Page 20

• Manufacturer Part Number: LM87CIMT/NOPB
• Description: IC INTERFACE SER MONITOR 24TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM87CIMT/NOPB

• Function: Hardware Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Speed Control, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: I²C™/SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 2.8 V ~ 3.8 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM87CIMT; *LM87CIMT/NOPB; LM87CIMT

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With the exception of the IRQ inputs and Hardware Temper-
ature errors, all interrupts are indicated in the two Interrupt
Status Registers. The INT# output has two mask registers,
and individual masks for each Interrupt. As described in Sec-
tion 3.3, the hardware Interrupt line can also be enabled/
disabled in the Configuration Register.
The THERM# interrupt output is dedicated to temperature
and therefore is only related to internal and external temper-
ature readings, and the Low, High and Hardware temperature
limits.
9.1 INT# Interrupts
The INT# system combines several groups of error signals
together into a common output. These groups are; IRQ inputs,
Voltage and Fan inputs, Temperature Values, and the
THERM# input. Each one of these groups or channels func-
tions a little differently.
The IRQ inputs provide the least complicated INT# operation.
The IRQ input block is enabled by setting bit 7of the Channel
Mode Register (16h) to 0. Then the individual inputs are en-
abled by setting the corresponding IRQ Enable bits to 1. If an
IRQ input is enabled, and subsequently an input signal is as-
serted on that channel, the INT# output will be asserted.
During the interrupt service routine, the INT# output can be
deasserted in a number of ways. The INT#_Clear bit can be
set during the ISR to prevent further interrupts from occurring.
Then the IRQ enable bit for the particular input can be cleared
to prevent that channel from causing further interrupts. At this
point the INT#_Clear bit can be cleared and no further inter-
rupts would be issued from this particular IRQ input. Once the
signal causing the IRQ has been removed, the enable bit for
that IRQ channel could be set again.
Voltage, Fan, and Temperature High/Low errors are slightly
more complex in their generation of INT# outputs. All of these
error bits are stored in the Interrupt Status Registers at 43h,
44h and the Interrupt Status Mirror Registers at 4Ch and 4Dh.
These inputs are gated by the Interrupt Mask Registers and
processed by the INT# state machine to generate the INT#
output.
Voltage and Fan error conditions are processed as follows.
Every time a round robin conversion cycle is completed, the
high/low limit comparisons for voltage and fan quantities are
updated. If a quantity is outside the limits, the appropriate In-
terrupt Status Register bit will be set. If the corresponding
Interrupt Mask Register bit is 0, then the Status Bit will cause
the INT# output to be asserted. Reading the Interrupt Status
the THERM# input is deactivated and the DAC setting
register is unaffected by the THERM# input condition.
IRQ0-2:
external interrupt source. If enabled via the Channel Mode
Register (16h) the INT# output will be activated whenever
these inputs are pulled low. Since there are no dedicated
ISR bits that correspond to the IRQ inputs, the VID status
bits can be read to determine which IRQ input is active.
Similarly, to mask off these inputs as interrupt sources,
they must be disabled via the Channel Mode Register
(16h).
IRQ3-4:
external interrupt source. If enabled via the Channel Mode
Register (16h) and Configuration Register 2 (4Ah), the
INT# output will be activated whenever these inputs are
driven high. Since there are no dedicated ISR bits that
correspond to the IRQ inputs, the VID status bits can be
read to determine which IRQ input is active. Similarly, to
mask off these inputs as interrupt sources, they must be
disabled via Configuration Register 2 (4Ah).
These are active low inputs from any type of
These are active high inputs from any type of
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register will clear the Status Bit and cause the INT# output to
be deasserted. If the parameter is still outside the limits on the
next conversion, the status bit will again be set and it will again
cause an interrupt. If, on a subsequent conversion cycle, the
parameter returns within the High/Low limits before the Inter-
rupt Status Registers are read, the Interrupt Status bit will
remain set and the INT# output will remain asserted.
Temperature High/Low errors are somewhat more complicat-
ed. The internal temperature value is compared with the
Internal Temperature High and Low Limits in Registers 39h
and 3Ah (and with the Internal Temperature Hardware High
Limit in Registers 13h and 17h, see the next paragraph for
details). We will begin with the temperature value initially
within the High/Low limits and the corresponding Interrupt
Mask Bit = 0. If the temperature value rises above the high
limit, or below the low limit, the corresponding Interrupt Status
Register bit will be set. This will then cause an INT# to be
asserted. Reading the Interrupt Status Register will clear the
status bit and cause INT# to be deasserted. If the temperature
value remains above the high limit during subsequent con-
version cycles, the Interrupt Status Bit will again be set, but
no new INT# will be generated from this source. INT# may be
reasserted if:
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The third group of signals that will generate INT# outputs are
Hardware Temperature errors, caused by temperatures ex-
ceeding the hardware limits stored at 13h, 14h, 17h, and
18h.The internal temperature value is compared with the In-
ternal Temperature Hardware High Limits in Registers 13h
and 17h. The external temperature values are compared with
the External Temperature Hardware High Limits in Registers
14h and 18h. The limits in Register 14h and 18h apply equally
to the values of both D1 and D2. Both temperature values are
individually compared with both limit values.
The only difference between the different Hardware Limit reg-
isters is that by writing a 1 into Bit 1 of register 4Ah, the
contents of register 13h will be locked and cannot be repro-
grammed. Similarly, the contents of register 14h will be locked
by writing a 1 into Bit 2 of register 4Ah. The registers can only
be reprogrammed if Bit 7 of Configuration Register 1 (40h) is
written to re-Initialize the chip, or power is removed and reap-
plied. This feature is provided to prevent software from unin-
tentionally overwriting these important limits.
Again, we will assume that the temperature initially is below
the Hardware Temperature setpoints. If the temperature on a
subsequent conversion is above any of the values stored in
the Hardware Temperature Limit registers, the INT# output
will be asserted. Errors caused by exceeding these limits
cannot be cleared by reading the Interrupt Status Registers,
and the INT# condition can only be cleared by clearing the
Thermal INT# Enable bit, by setting the INT#_Clear bit or by
disabling INT# by clearing the INT#_Enable bit.
The final INT# source to consider is the THERM# input/out-
put. THERM# can be pulled low by an external source to
generate an INT# output. Pulling THERM# low with external
circuitry sets the corresponding THERM# Interrupt Status Bit.
If this bit is not masked, it will cause INT# to be asserted.
The temperature then transitions up or down through the
opposite limit to that originally exceeded.
The original limit crossed is programmed to a new value
and on a subsequent conversion cycle, the converted
temperature is outside the new limit. This would cause the
corresponding Interrupt Status Bit to be set, causing a new
INT# event.
An interrupt is generated by any other source, including
any other temperature error or the THERM# pin being
pulled low by an external signal.