LM92CIM/NOPB National Semiconductor, LM92CIM/NOPB Datasheet - Page 10

• Manufacturer Part Number: LM92CIM/NOPB
• Description: IC SENSOR/THERM COMP DIG 8-SOIC
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM92CIM/NOPB

• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Comparator, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -55°C ~ 150°C
• Output Type: I²C™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -55°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM92CIM; *LM92CIM/NOPB; LM92CIM

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1.5 SHUTDOWN MODE
Shutdown mode is enabled by setting the shutdown bit in the
Configuration register via the Serial Bus. Shutdown mode re-
duces power supply current to 5 μA typical. T_CRIT_A is reset
if previously set. Since conversions are stoped during shut-
down, T_CRIT_A and INT will not be operational. The Serial
Bus interface remains active. Activity on the clock and data
lines of the Serial Bus may slightly increase shutdown mode
quiescent current. Registers can be read from and written to
in shutdown mode. The LM92 takes miliseconds to respond
to the shutdown command.
1.6 INT AND T_CRIT_A OUTPUT
The INT and T_CRIT_A outputs are open-drain outputs and
do not have internal pull-ups. A "high" level will not be ob-
1.8 INTERNAL REGISTER STRUCTURE
There are four data registers in the LM92, selected by the
Pointer register. At power-up the Pointer is set to “00”; the
location for the Temperature Register. The Pointer register
latches the last location it was set to. In Interrupt Mode, a read
from the LM92 resets the INT output. Placing the device in
Shutdown mode resets the INT and T_CRIT_A outputs. All
registers are read and write, except the Temperature register
which is read only.
A write to the LM92 will always include the address byte and
the Pointer byte. A write to the Configuration register requires
one data byte, while the T
require two data bytes.
Reading the LM92 can take place either of two ways: If the
location latched in the Pointer is correct (most of the time it is
expected that the Pointer will point to the Temperature regis-
ter because it will be the data most frequently read from the
LM92), then the read can simply consist of an address byte,
LOW
, T
HIGH
, and T_CRIT registers
10
served on these pins until pull-up current is provided from
some external source, typically a pull-up resistor. Choice of
resistor value depends on many system factors but, in gen-
eral, the pull-up resistor should be as large as possible. This
will minimize any errors due to internal heating of the LM92.
The maximum resistance of the pull up, based on LM92 spec-
ification for High Level Output Current, to provide a 2 volt high
level, is 30K ohms.
1.7 FAULT QUEUE
A fault queue of 4 faults is provided to prevent false tripping
when the LM92 is used in noisy environments. The 4 faults
must occur consecutively to set flags as well as INT and
T_CRIT_A outputs. The fault queue is enabled by setting bit
4 of the Configuration Register high (see Section 1.11).
followed by retrieving the corresponding number of data
bytes. If the Pointer needs to be set, then an address byte,
pointer byte, repeat start, and another address byte plus re-
quired number of data bytes will accomplish a read.
The first data byte is the most significant byte with most sig-
nificant bit first, permitting only as much data as necessary to
be read to determine the temperature condition. For instance,
if the first four bits of the temperature data indicates a critical
condition, the host processor could immediately take action
to remedy the excessive temperature. At the end of a read,
the LM92 can accept either Acknowledge or No Acknowledge
from the Master (No Acknowledge is typically used as a signal
for the slave that the Master has read its last byte).
An inadvertent 8-bit read from a 16-bit register, with the D7
bit low, can cause the LM92 to stop in a state where the SDA
line is held low as shown in
further bus communication until at least 9 additional clock cy-
Figure
4. This can prevent any
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