ISL6595DRZ Intersil, ISL6595DRZ Datasheet - Page 10

• Manufacturer Part Number: ISL6595DRZ
• Description: IC DIGITL MULTIPHASE CTRLR 48QFN
• Manufacturer: Intersil

Specifications of ISL6595DRZ

• Applications: Digital Multiphase Controller
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

• Digital Control Loop and AVP – An over-sampled digital
• Window comparators – Window comparators with fixed
• Active Transient Response (ATR) – ATR comparators
• Configurable PWM Generators – 1 to 6 PWM
• Integrated NVM - Digital configuration is stored in an
• Serial Interface – Intersil PowerCode software provides
The Intersil PowerCode interface allows full accessibility to
regulator telemetry during system operation including:
• Internal Controller Temperature
• External (via optional thermistor) System Temperature
• Per Phase Current
• Total Output Current
• Output Voltage
• Input Voltage
• Configurable latched and unlatched individual fault status
• Microprocessor Leakage Current
• User Defined Memory Space
Fault reporting and shutdown behavior are also fully
configurable. Two individual fault outputs are provided
(FAULT1, FAULT2), both of which can be masked
independently. The outputs can be configured as either
Proportional-Integral-Derivative (PID) compensator
provides flexible loop compensation with programmable
coefficients. A digital post-filter provides additional phase
lead and/or high frequency filtering to optimize the
transient response and ripple of the system. A high
accuracy Active Voltage Positioning (AVP) loadline is
computed using the calibrated current sense
measurements. The AVP bandwidth is also programmable
to allow it to be optimized for dynamic performance.
thresholds for input undervoltage lockout (IUVP), output
undervoltage and overvoltage protection (OUVP and
OOVP). In addition a second OOVP comparator is
provided with a programmable threshold with respect to
the VID.
with programmable thresholds are used to provide fast
response to dynamic load transients, minimizing spike
overshoot and droop undershoot.
waveforms are digitally generated ensuring low jitter and
high linearity. PWM outputs are configurable as either
single tri-valent outputs or dual outputs with
programmable non-overlap delay. Phases can be fully
overlapped, with programmable duty cycle limiting.
integrated NVM, allowing fully independent (stand-alone)
operation. NVM is fully accessible to user so that a
completely new parameter set can be written. Vendor and
user defined memory locations are provided, allowing
version control and part identification. NVM integrity is
checked every configuration cycle through a cyclic
redundancy check (CRC) comparison.
easy access to all configuration, telemetry, and testability
features over a 2 wire I
2
C serial interface.
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ISL6595
latched or unlatched, active high or active low polarity, and
CMOS or open drain outputs. The shutdown operation also
allows all faults to be individually masked and for the
shutdown operation to be either latched or unlatched.
Individual status registers allow fault reporting over the serial
bus to identify the specific fault event. Fault detection
includes the following:
• Input Undervoltage (IUVP)
• Output Overvoltage (OOVP)
• Output Undervoltage (OUVP)
• Per Phase Overcurrent
• Total Output Overcurrent (OCP)
• Two levels of Internal Temperature Protection
• Four levels of External Temperature Protection
• Configuration Failure
• Calibration Time-out Failure
Theory of Operation
Power-Up and Initialization
The ISL6595 is designed to provide supply sequence
independence and graceful turn-on and turn-off operation. It
operates from a single +3.3V supply, while an on-chip low
drop-out (LDO) regulator generates an internal +2.5V
supply. Power-up controller configuration is initialized by
either an internal threshold based power-on reset, or by an
external reset pin (RESET_N). During controller
configuration, the contents of the NVM are read into the
controller’s registers. During configuration, all outputs are
three-stated, allowing board pull-up or pull-down resistors to
set the correct default level.
Once configuration is completed, the controller enters an
inactive state. Outputs assume their default values, which
may be low, high or three-state. During the inactive state, the
controller can communicate over the serial bus, report
configuration or inactive state faults. The controller will leave
the inactive state and begin soft-start once it has a valid VID,
VR_EN is asserted, and the 12V power input is valid. The
12V input is sensed through a resistive divider on the board,
and a fixed threshold comparator must be tripped if the input
undervoltage lockout is enabled. The sense circuit can be
easily modified to also sense an independent or sequenced
lower drive voltage typically used to optimize the efficiency of
the power stage low side FET.
Soft-Start and Calibration
Prior to entering an active regulating state, the ISL6595
performs a well-controlled, monotonic initial ramp or
“soft-start”. Soft-start is performed by actively regulating the
load voltage while digitally ramping the target voltage from
0 to the voltage set. During this time, the optional power-up
system calibration can be performed. The calibration
December 4, 2008
FN9192.2