MAX16063TG+ Maxim Integrated Products, MAX16063TG+ Datasheet - Page 11

• Manufacturer Part Number: MAX16063TG+
• Description: IC PWR MNTR/OVRVOLT PROT 24TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX16063TG+

• Applications: Power Supply Monitor, Overvoltage Protection
• Voltage - Supply: 1 V ~ 5.5 V
• Current - Supply: 45µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RESET asserts low when the voltage on any of the
UVIN_ inputs falls below its respective threshold, the
voltage on any of the OVIN_ inputs goes above its
respective threshold, or MR is asserted. RESET
remains asserted for the reset timeout period after all
monitored UVIN_ inputs exceed their respective thresh-
olds, all OVIN_ inputs fall below their respective thresh-
olds, and MR is deasserted (see Figure 6). This
open-drain output has a 30µA internal pullup.
The reset timeout period can be adjusted to accommo-
date a variety of microprocessor (µP) applications.
Adjust the reset timeout period (t
capacitor (C
reset timeout capacitor as follows:
Figure 5. Interfacing to a Different Logic Supply Voltage
MAX16063
V
V
SRT
CC
CC
GND
= 3.3V
) between SRT and GND. Calculate the
C
SRT
UVOUT_
______________________________________________________________________________________
( )
F
Reset Timeout Capacitor
=
⎛
⎜
⎝
V
TH SRT
t
100kΩ
RP
I
SRT
_
( )
RESET
s
RP
⎞
⎟
⎠
) by connecting a
RESET Output
V
GND
5V
Quad Window Voltage Detector
CC
1% Accurate, Low-Voltage,
Connect SRT to V
timeout of 140ms (min).
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts RESET low. RESET remains asserted while MR
is low, and during the reset timeout period (140ms min)
after MR returns high. The MR input has an internal
20kΩ pullup resistor to V
not used. MR can be driven with TTL or CMOS-logic
levels, or with open-drain/collector outputs. Connect a
normally open momentary switch from MR to GND to
create a manual reset function; external debounce cir-
cuitry is not required. If MR is driven from long cables
or if the device is used in a noisy environment, connect-
ing a 0.1µF capacitor from MR to GND provides addi-
tional noise immunity.
Figure 6. Output Timing Diagram
OVOUT_
UVOUT_
UVIN_
RESET
OVIN_
V
V
TH_
TH_
t
t
t
CC
RD
D
D
10%
10%
10%
for a factory-programmed reset
Manual Reset Input ( MR )
CC
, so it can be left open if it is
t
t
D
D
90%
90%
t
RP
V
V
TH_
TH_
+ V
- V
TH_HYS
TH_HYS
90%
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