ISL6506BCBZA Intersil, ISL6506BCBZA Datasheet - Page 5
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ISL6506BCBZA
Manufacturer Part Number
ISL6506BCBZA
Description
IC PWR SUPPLY CTRLR/MONITR 8SOIC
Manufacturer
Intersil
Datasheet
1.ISL6506BCBZ.pdf
(8 pages)
Specifications of ISL6506BCBZA
Applications
Power Supply Controller/Monitor
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
3.6mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width) Exposed Pad, 8-eSOIC. 8-HSOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Input
-
Soft-Start
Figures 3 and 4 show the soft-start sequence for the typical
application start-up into a sleep state. At time t0, 5V
is applied to the circuit. At time t1, the 5V
level. Time t2, one soft-start interval after t1, denotes the
initiation of soft-start. The 3.3V
through the internal standby LDO through an internal digital
soft-start function. Figure 4 shows the 5V
soft-start at time t2 as well. The ISL6506A will draw 7.5µA
into the 5VDLSB for a duration of one soft-start period. This
current will enhance the P-MOSFET (Q
Application” on page 2) in a controlled manner. At time t3,
the 3.3V
down to ground. If the 5V
of the 5V
sudden step as the P-MOSFET gate is fully enhanced. The
soft-start profile of the 5V
capacitor between the gate and drain of the P-MOSFET.
Adding this capacitor will increase the gate capacitance and
slow down the start of the 5V
At time t4, the system has transitioned into S0 state and the
ATX supplies have begun to ramp-up. With the ISL6506,
ISL6506B (Figure 3), the 5V
from the 5V
(Q
regulation (Figure 4). At time t5, the 12V
surpassed the 12V POR level. Time t6 is three soft-start
cycles after the 12V POR level has been surpassed. At time
t6, three events occur simultaneously. The DLA pin is forced
to a high impedance state which allows the 12V rail to
enhance the two N-MOSFETs (Q
ATX rails to the 3.3V
is actively pulled high, which will turn the P-MOSFET (Q
Finally, the internal LDO which regulates the 3.3V
sleep states is put in standby mode.
3.3V, 5V, 12V
3
). The ISL6506A will already have the 5V
5VDLSB
FIGURE 2. 5V
3V3DL
5VSB
5VDL
DLA
DUAL
S3
S5
SB
ATX
rail by time t3, then the rail will experience a
is in regulation and the 5VDLSB pin is pulled
ISL6506A
rail through the body diode of the N-MOSFET
DUAL
DUAL
AND 3.3V
DUAL
DUAL
and 5V
DUAL
DUAL
5
DUAL
rail has not reached the level
may be altered by placing a
AUX
1
DUAL
rail will begin to ramp-up
and Q
rail.
TIMING DIAGRAM;
rail is brought up
rails. The 5VDLSB pin
ATX
2
3
DUAL
, refer to “Typical
SB
) that connect the
rail has
DUAL
ISL6506, ISL6506A, ISL6506B
surpasses POR
rail initiating a
AUX
rail in
SB
rail in
(bias)
2
) off.
Sleep to Wake State Transitions
Figures 3 and 4, starting at time t4, depict the transitions
from sleep states to the S0 wake state. Figure 3 shows the
transition of the ISL6506, ISL6506B from the S4/S5 state to
the S0 state. Figure 4 shows how the ISL6506, ISL6506B
will transition from the S3 sleep state into S0 state. Figure 3
also shows how the ISL6506A transitions from either S3 or
S4/S5 in the S0 state. For all transitions, t4 depicts the
system transition into the S0 state. Here, the ATX supplies
are enabled and begin to ramp up. At time t5, the 12V
has exceeded the POR threshold for the ISL6506, ISL6506B
and ISL6506A. Three soft-start periods after time t5, at time
t6, three events occur simultaneously. The DLA pin is forced
0V
0V
FIGURE 4. SOFT-START INTERVAL FOR ISL6506A IN S4/S5
FIGURE 3. ISL6506 AND ISL6506B SOFT-START INTERVAL
t0
t0
(1V/DIV)
(1V/DIV)
5VSB
5VSB
5VDLSB
t1
(5V/DIV)
t1
AND S5 TO S0 TRANSITION FOR ISL6506A AND
S3 TO S0 TRANSITION FOR ISL6506, ISL6506A,
ISL650B
IN S4/S5 STATE AND S5 TO S0 TRANSITION
t2
t2
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
5VDUAL
(1V/DIV)
t3
t3
TIME
TIME
t4
t4
t5
t5
5VDUAL
(1V/DIV)
(10V/DIV)
(10V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
DLA
DLA
3.3VDUAL
(2V/DIV)
October 21, 2010
3.3VDUAL
(2V/DIV)
t6
ATX
t6
FN9141.4
rail