MAX16066ETL+ Maxim Integrated Products, MAX16066ETL+ Datasheet - Page 47

• Manufacturer Part Number: MAX16066ETL+
• Description: IC SYSTEM MANAGER 8CH 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX16066ETL+

• Applications: Power Supply Monitor, Sequencer
• Voltage - Supply: 2.8 V ~ 14 V
• Current - Supply: 4.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Number Of Voltages Monitored: 8
• Undervoltage Threshold: 2.7 V
• Manual Reset: Resettable
• Watchdog: Yes
• Battery Backup Switching: No
• Power-up Reset Delay (typ): 200 us
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10 mA
• Maximum Power Dissipation: 2105 mW
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Chip Enable Signals: No
• Internal Hysteresis: Yes
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure
12-Channel/8-Channel, Flash-Configurable System
Pause-DR: Shifting of the test data registers halts while
in this state. All test data registers retain their previous
state. The controller remains in this state while TMS is
low. A rising edge on TCK with TMS high puts the con-
troller in the exit2-DR state.
Exit2-DR: A rising edge on TCK with TMS high while
in this state puts the controller in the update-DR state.
A rising edge on TCK with TMS low enters the shift-DR
state.
Update-DR: A falling edge on TCK while in the update-
DR state latches the data from the shift register path of
the test data registers into a set of output latches. This
prevents changes at the parallel output because of
15. JTAG Block Diagram
TMS
TCK
TDI
R
PU
V
DB
Managers with Nonvolatile Fault Registers
______________________________________________________________________________________
MEMORY ADDRESS REGISTER
MEMORY WRITE REGISTER
MEMORY READ REGISTER
IDENTIFICATION REGISTER
INSTRUCTION REGISTER
USER CODE REGISTER
TEST ACCESS PORT
(TAP) CONTROLLER
[LENGTH = 32 BITS]
[LENGTH = 5 BITS]
[LENGTH = 8 BITS]
[LENGTH = 8 BITS]
[LENGTH = 32 BITS]
[LENGTH = 8 BITS]
BYPASS REGISTER
[LENGTH = 1 BIT]
AND FLASH
REGISTERS
changes in the shift register. On the rising edge of TCK,
the controller goes to the run-test/idle state if TMS is low
or goes to the select-DR-scan state if TMS is high.
Select-IR-Scan: All test data registers retain the previ-
ous states. The instruction register remains unchanged
during this state. With TMS low, a rising edge on TCK
moves the controller into the capture-IR state. TMS high
during a rising edge on TCK puts the controller back into
the test-logic-reset state.
Capture-IR: Use the capture-IR state to load the shift
register in the instruction register with a fixed value.
This value is loaded on the rising edge of TCK. If TMS is
high on the rising edge of TCK, the controller enters the
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00000
11111
MUX 1
COMMAND
DECODER
MUX 2
01001
01010
01011
01100
01000
00111
SETFLSHADD
RSTUSRFLSH
SAVE
RSTFLSHADD
SETUSRFLSH
REBOOT
TDO
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