IR3505MPBF International Rectifier, IR3505MPBF Datasheet - Page 11

• Manufacturer Part Number: IR3505MPBF
• Description: IC XPHASE3 CONTROL 16-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase3™r

Specifications of IR3505MPBF

• Applications: Processor
• Current - Supply: 3mA
• Voltage - Supply: 8 V ~ 16 V
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-MLPQ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IR3505 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3505 is shown in Figure 5, and specific features are discussed in the following sections.
Tri-State Gate Drivers
The gate drivers can deliver up to 2A peak current (4A sink current for bottom driver). An adaptive non-overlap
circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-through current while
minimizing body diode conduction. The non-overlap latch is added to eliminate the error triggering caused by the
switching noise. An enable signal is provided by the control IC to the phase IC without the addition of a dedicated
signal line. The error amplifier output of the control IC drives low in response to any fault condition such as VCCL
under voltage or output overload. The IR3505 Body Braking
output low. This tri-state operation prevents negative inductor current and negative output voltage during power-
down.
A synchronous rectification disable comparator is used to detect converter CSIN- pin voltage, which represents
local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected, GATEL drives
low, which disables synchronous rectification and eliminates negative current during power-up.
The gate drivers pull low if the supply voltages are below the normal operating range. An 80k
across the GATEH/GATEL and PGND pins to prevent the GATEH/GATEL voltage from rising due to leakage or
other causes under these conditions.
PHSIN
ISHARE
DACIN
EAIN
CLKIN
LGND
VCC
Page 11 of 19
100% DUTY LATCH
PWM_CLK
PWM_CLK
PWMQ
PWM COMPARATOR
SHARE_ADJ
DACIN
(LOW=OPEN)
DEBUG OFF
DACIN-SHARE_ADJ
CALIBRATION
CLK
D
+
-
CALIBRATION
Q
-
+
RMPOUT
SHARE
ADJUST
AMPLIFIER
PHSIN
VCC
VCCL
100mV
200mV
0.8V
PHSIN
+
-
PWM RAMP
GENERATOR
(CLKIN IF 1-PHASE)
OVP
COMPARATOR
BODY BRAKING
COMPARATOR
3K
+
-
-
+
NEGATIVE CURRENT
COMPARATOR
RESET
DOMINANT
PWM RESET
PWM LATCH
NEGATIVE
CURRENT
LATCH
PWM_CLK
PWM_CLK
-
+
Q
VCCL
RESET
DOMINANT
R
Figure 5 Block diagram
S
D
CLK
Q
Q
PWMQ
IROSC
GATEL NON-
OVERLAP
LATCH
GATEH NON-
OVERLAP
LATCH
CLK
D
TM
SET
DOMINANT
SET
DOMINANT
Q
Q
Q
comparator detects this and drives bottom gate
R
R
S
S
SYNCHRONOUS RECTIFICATION
DISABLE COMPARATOR
DACIN
+
IROSC
+
CSAOUT
-
+
GATEH NON-
OVERLAP
COMPARATOR
GATEL NON-
OVERLAP
COMPARATOR
X
0.75
CURRENT SENSE
AMPLIFIER
-
+
+
-
GATEL
DRIVER
X33
1V
1V
CALIBRATION
GATEH
DRIVER
-
+
Sept 26
DEBUG
COMPARATOR
resistor is connected
-
+
th
, 2007
IR3505
0.2V
PHSOUT
BOOST
GATEH
SW
VCCL
GATEL
PGND
CSIN-
CSIN+