IR3081AMPBF International Rectifier, IR3081AMPBF Datasheet - Page 17

• Manufacturer Part Number: IR3081AMPBF
• Description: IC CTRLR XPHASE VR10.0 28MLPQ
• Manufacturer: International Rectifier
• Series: XPhase™r

Specifications of IR3081AMPBF

• Applications: Processor
• Current - Supply: 11mA
• Voltage - Supply: 9.5 V ~ 14 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 28-MLPQ
• Package: 28-Lead MLPQ
• Circuit: X-Phase Controller IC
• Switch Freq (khz): 150kHz to 1.0MHz
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Good Output
The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During
soft start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.71V. The
PWRGD pin becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in
operation and has no fault, but does not ensure the output voltage is within the specification. Output voltage
regulation within the design limits can logically be assured however, assuming no component failure in the system.
Load Current Indicator Output
The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current can
be retrieved by a differential amplifier which subtracts the VDAC voltage from the VDRP voltage.
System Reference Voltage (VBIAS)
The IR3081 supplies a 6.8V/5mA precision reference voltage from the VBIAS pin. The oscillator ramp amplitude
tracks the VBIAS voltage, which should be used to program the Phase IC trip points to minimize phase delay errors.
Precondition of IIN during Soft Start
IIN pin is clamped during the early stage of soft start, which disables current sharing function in the phase ICs to
prevent PWM ramp from pulling too low. When V(SS/DEL)<0.7V, the precondition latch is set, and IIN is clamped
to ground through a 10kΩ resistor. After V(SS/DEL) is 1.3V above V(FB), error amplifier output is released. When
V(EAOUT) jumps above 0.6V, the precondition latch is reset and the IIN clamp is removed. Normal current
sharing in the phase ICs then resumes.
VCC
(12V)
ENABLE
SS/DEL
VOUT
PWRGD
IOUT
Page 17 of 39
(ENABLE GATES
FAULT MODE)
3.685V
3.735V
1.3V
START-UP
(VOUT CHANGES DUE TO LOAD
AND VID CHANGES)
NORMAL OPERATION
OCP THRESHOLD
Figure 10. Operating Waveforms
OCP
DELAY
HICCUP OVER-CURRENT
PROTECTION
RE-START
AFTER
OCP
IR3081A
1/31
/05
POWER-DOWN
(VCC GATES
FAULT MODE)
8.9V
UVLO