IR3081M International Rectifier, IR3081M Datasheet

IC PHASE CONTROLLER 28-MLPQ

IR3081M

Manufacturer Part Number
IR3081M
Description
IC PHASE CONTROLLER 28-MLPQ
Manufacturer
International Rectifier
Series
XPhase™r
Datasheet

Specifications of IR3081M

Applications
Processor
Current - Supply
11mA
Voltage - Supply
9.5 V ~ 14 V
Operating Temperature
0°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
28-MLPQ
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*IR3081M

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IR3081M
Manufacturer:
IR
Quantity:
20 000
Company:
Part Number:
IR3081MTRPBF
Quantity:
3 000
DESCRIPTION
FEATURES
PACKAGE PINOUT
Page 1 of 39
The IR3081 Control IC combined with an IR XPhase
to implement a complete VR 10 power solution. The “Control” IC provides overall system control and
interfaces with any number of “Phase ICs” which each drive and monitor a single phase of a multiphase
converter. The XPhase
to design while providing higher efficiency than conventional approaches.
The IR3081 is intended for VRD or VRM/EVRD 10 applications that use external VCCVID/VTT circuits.
6 bit VR 10 compatible VID with 0.5% overall system accuracy
1 to X phases operation with matching phase ICs
Programmable Dynamic VID Slew Rate
No Discharge of output capacitors during Dynamic VID step-down (can be disabled)
+/-300mV Differential Remote Sense
Programmable 150kHz to 1MHz oscillator
Programmable VID Offset and Load Line output impedance
Programmable Softstart
Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
Simplified Powergood provides indication of proper operation and avoids false triggering
Operates from 12V input with 9.1V Under-Voltage Lockout
6.8V/5mA Bias Regulator provides System Reference Voltage
Enable Input
Small thermally enhanced 28L MLPQ package
TM
DESIGNS. REPLACE WITH IR3081A
NOT RECOMMENDED FOR NEW
architecture results in a power supply that is smaller, less expensive, and easier
1
2
3
4
5
6
7
OSCDS
VID5
VID0
VID1
VID2
VID3
VID4
IR3081
CONTROL
IC
TM
Phase IC provides a full featured and flexible way
XPHASE
EAOUT
OCSET
VBIAS
VDRP
BBFB
FB
IIN
21
20
19
18
17
16
15
TM
Data Sheet No.PD94706
VR 10 CONTROL IC
10/01
IR3081
/04

Related parts for IR3081M

IR3081M Summary of contents

Page 1

DESIGNS. REPLACE WITH IR3081A DESCRIPTION The IR3081 Control IC combined with an IR XPhase to implement a complete VR 10 power solution. The “Control” IC provides overall system control and interfaces with any number of “Phase ICs” which each drive ...

Page 2

... ORDERING INFORAMATION Device IR3081MTR * IR3081M * Samples only ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..150 Storage Temperature Range………………….-65 ESD Rating………………………………………HBM Class 1C JEDEC standard ...

Page 3

ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 9.5V ≤ V PARAMETER VDAC Reference System Set-Point Accuracy Source Current Sink Current VID Input Threshold VID Input Bias Current Regulation Detect Comparator Input Offset Regulation Detect to EAOUT Delay BBFB ...

Page 4

PARAMETER Oscillator Switching Frequency Peak Voltage (5V typical, measured VBIAS) Valley Voltage (1V typical, measured VBIAS) VBIAS Regulator Output Voltage Current Limit Soft Start and Delay SS/DEL to FB Input Offset Voltage Charge Current ...

Page 5

PIN DESCRIPTION PIN# PIN SYMBOL PIN DESCRIPTION 1 OSCDS Apply a voltage greater than VBIAS to disable the oscillator. Used during factory testing & trimming. Ground or leave open for normal operation. 2-7 VID0-5 Inputs to VID ...

Page 6

SYSTEM THEORY OF OPERATION TM XPhase Architecture TM The XPhase architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can control ...

Page 7

PWM Control Method The PWM block diagram of the XPhase trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the ...

Page 8

VPEAK (5.0V) VPHASE4&5 (4.5V) VPHASE3&6 (3.5V) VPHASE2&7 (2.5V) VPHASE1&8 (1.5V) VVALLEY (1.00V) PWM Operation The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set; the PWMRMP voltage begins to increase; the ...

Page 9

PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; The ...

Page 10

Figure 5. Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled ...

Page 11

IR3081 THEORY OF OPERATION Block Diagram The Block diagram of the IR3081 is shown in Figure 6, and specific features are discussed in the following sections. VCC - START + STOP + VCC UVLO 9.1V COMPARATOR 8.9V - ENABLE ENABLE ...

Page 12

The IR3081 can accept changes in the VID code while operating and vary the DAC voltage accordingly. The sink/source capability of the VDAC buffer amplifier is programmed by the same external resistor that sets the oscillator frequency. The slew rate ...

Page 13

Processor Pins (0 = low high) VID4 VID3 VID2 VID1 ...

Page 14

Control IC VDAC Inductor DCR Temperature Correction If the thermal compensation of the inductor DCR provided by the temperature dependent gain of the current sense amplifier is not adequate, a negative temperature coefficient (NTC) thermistor can be used for additional ...

Page 15

Soft Start, Over-Current Fault Delay, and Hiccup Mode The IR3081 has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor connected between the SS/DEL and LGND pins controls soft start as well as over-current ...

Page 16

VCC (12V) ENABLE 3.91V SS/DEL 1.3V VOUT PWRGD IOUT START-UP NORMAL OPERATION (ENABLE GATES (VOUT CHANGES DUE TO LOAD FAULT MODE) AND VID CHANGES) Power Good Output The PWRGD pin is an open-collector output and should be pulled up to ...

Page 17

APPLICATION INFORMATION 12V RVCC 10 ohm CVCC 0.1uF 1nF 0.1uF ENABLE 1 OSCDS VBIAS 2 VID5 VID5 BBFB IR3081 VID0 3 VID0 EAOUT CONTROL VID1 4 VID1 FB IC VID2 5 VID2 VDRP VID3 6 VID3 IIN VID4 7 VID4 ...

Page 18

DESIGN PROCEDURES - IR3081 AND IR3086 CHIPSET IR3081 EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3081 generates a triangle waveform to synchronize the phase ICs, and the switching frequency of the each phase converter equals the oscillator frequency, which ...

Page 19

VDAC down-slope and is given by Equation (9), where I shown in Figure15. I SINK = C VDAC SR DOWN = + VDAC I SOURCE = VDAC Over Current Setting ...

Page 20

MAX = R FB ∗ DRP TM Body Braking Related Resistors R TM The body braking during Dynamic VID can be disabled by connecting BBFB pin to ground. If the feature is ...

Page 21

Over Temperature Setting Resistors R The threshold voltage of VRHOT comparator is proportional to the die temperature T the relationship between the die temperature of phase IC and the temperature of the power converter according to the power loss, PCB ...

Page 22

If the over temperature setting voltage is higher than the phase delay setting voltage, VBIAS*RA HOTSET pin between R and R PHASEx1 respectively. Pre-select R PHASEx1 ( V HOTSET = R PHASEx PHASEx R PHASEx 3 Bootstrap ...

Page 23

∗ optional and may be needed in some applications to reduce the jitter caused by the high frequency ...

Page 24

π ∗ ∗ π ∗ π ∗ ∗ ...

Page 25

DESIGN EXAMPLE 1 - VRM 10 2U CONVERTER SPECIFICATIONS Input Voltage DAC Voltage: V =1.35 V DAC No Load Output Voltage Offset: V Output Current: I =105 ADC O Maximum Output Current: I =120 ADC OMAX ...

Page 26

VDAC Slew Rate Programming Capacitor C From Figure 15, the sink current of VDAC pin corresponding to 400kHz (R VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate. − SINK = = C ...

Page 27

Body Braking Related Resistors R N/A. The body braking during Dynamic VID is disabled. IR3086 EXTERNAL COMPONENTS PWM Ramp Resistor R and Capacitor C PWMRMP Set PWM ramp magnitude V PWMRMP resistor R , PWMRMP = R PWMRMP ∗ ∗ ...

Page 28

Bootstrap Capacitor C BST Choose C =0.1uF BST Decoupling Capacitors for Phase IC and Power Stage Choose C =0.1uF, C =0.1uF VCC VCCL VOLTAGE LOOP COMPENSATION Type II compensation is used for the converter with AL-Polymer output capacitors. Choose the ...

Page 29

DESIGN EXAMPLE 2 - EVRD 10 HIGH FREQUENCY ALL-CERAMIC CONVERTER SPECIFICATIONS Input Voltage DAC Voltage: V =1.3 V DAC No Load Output Voltage Offset: V Output Current: I =105 ADC O Maximum Output Current: I =120 ...

Page 30

VDAC Slew Rate Programming Capacitor C From Figure 15, the sink current of VDAC pin corresponding to 800kHz (R VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate. − 170 * 10 SINK = = C ...

Page 31

Body Braking Related Resistors R N/A. The body braking during Dynamic VID is disabled. IR3086 EXTERNAL COMPONENTS PWM Ramp Resistor R and Capacitor C PWMRMP Set PWM ramp magnitude V PWMRMP resistor R , PWMRMP = R PWMRMP V * ...

Page 32

The over temperature setting voltage of Phases 3 and 4 is higher than the phase delay setting voltage, VBIAS*RA Pre-select R PHASEx. PHASEX1 − ∗ HOTSET PHASE 3 BIAS = R PHASE 32 − ...

Page 33

PWMRMP PWMRMP SW PWMRMP = F MI − − − PWMRMP DAC ...

Page 34

LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane LGND. • ...

Page 35

PCB Metal and Component Placement • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part ...

Page 36

Solder Resist • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...

Page 37

Stencil Design • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...

Page 38

PERFORMANCE CHARACTERISTICS Page Figure 13 - Oscillator Frequency versus ROSC 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 250 200 150 ...

Page 39

PACKAGE INFORMATION 28L MLPQ ( Body) – θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 www.irf.com Page C/W, θ JA Data and specifications subject ...

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