STW4810CRAT/LF ST-Ericsson Inc, STW4810CRAT/LF Datasheet - Page 34

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STW4810CRAT/LF

Manufacturer Part Number
STW4810CRAT/LF
Description
IC PWR MNGMNT MULTIMEDIA 84VFBGA
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of STW4810CRAT/LF

Applications
Processor
Current - Supply
170µA
Voltage - Supply
2.7 V ~ 4.8 V
Operating Temperature
-30°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
84-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STW4810CRAT/LF
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Part Number:
STW4810CRAT/LF
Manufacturer:
ST
0
STw4810
4.2.6
4.2.7
Note:
Figure 9.
CONTROL_SWITCH
MASTER_DIV_CLK
STEP_DOWN_CLK
MASTER_CLK_OK
* Phase delay is less than 90 between int and ext clock
PDN_INT_OSC
INT_OSC_OK
INT_OSC
IT generation
STw4810 has three interrupt balls:
IT_WAKE_UP: with only VBAT supply, no other supply available, when a USB cable is
plugged this interrupt is activated to wake up the host or the modem, depends of application
(active low).
USBINTn: This interrupt ball is dedicated to USB protocol and sent to multimedia processor
VDDOK: This ball has two functions:
- When high, it indicates that VIO_VMEM and VCORE output voltages are within the right
range and that the device internal temperature is below the maximum allowed temperature.
- When low, it indicates that output regulators (VCORE or VIO_VMEM) are not regulated
properly or PWREN = “0”, or that the temperature is above the allowed threshold (see
Thermal shut-down
11h) needs to be checked.
Clock switching and control
This block generates the clock used by the DC/DC converter (USB charge pump, step-down
VIO_VMEM and step-down VCORE). STw4810 is able to sustain the master clock
frequencies of 26 MHz, 19.2MHz and 13 MHz. It can also sustain dedicated MASTER_CLK
signal in the frequency range of 750KHz to 1MHz. If the clock is not detected the internal
oscillator is automatically selected.
When present the Master clock should remain connected up to sleep mode.
Clock switching between master and internal clock (1)
PON
internal clock
section). The interruption source in the application register (address
transition
external clock
Third rising edge after switching
Functional description
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